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Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Andy Lutomirski , Dave Hansen , Sergio Lopez , Peter Gonda , Peter Zijlstra , Srinivas Pandruvada , David Rientjes , tony.luck@intel.com, npmccallum@redhat.com, Brijesh Singh Subject: [PATCH Part1 RFC v3 07/22] x86/sev: Add a helper for the PVALIDATE instruction Date: Wed, 2 Jun 2021 09:04:01 -0500 Message-Id: <20210602140416.23573-8-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210602140416.23573-1-brijesh.singh@amd.com> References: <20210602140416.23573-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.9 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: =?utf-8?q?LZSGvdSFpm692t+7hHvtgXIdNFJIY2?= =?utf-8?q?sCBz85q0nPrhoyxB7UIDWNGPYv+f8euykGyB5wR4dUwVT/o7B4sE1fUNVj6SfQxKC?= =?utf-8?q?crAuXlIBdJFmllribpzZ/Uxabwe7e6ccdFxDTFKuwu4SP3cIvAEIWhPmqXVcwh8Pg?= =?utf-8?q?64ti4jT/vXTQspGYCS7ID9XczzM8vC6c+6XJkDb1Oa2i9aayCMhNMwYetsBTvCh1I?= =?utf-8?q?McS9J2BY5WXqK4hcig06F02sf3bDV75YQi5nRyBmNOjjtKGKZnR5Keg248QCKFREu?= =?utf-8?q?6Ddix0k8LVVVR0nTowmrUIy138sSh4jDLfVwFCBs5CTAhEFeEds7ye4H6kM0P1cTH?= =?utf-8?q?VAv9XRYcVQqfZZW52E+Irn2SYXGvZWwKy3eOCmdn9Lsfrlqzw62HyKkSms5h3Vvbv?= =?utf-8?q?qbkE0sgfQXrtGxHfts6VGPb+1UrG6LYRrtiG1kRzmSzE+9dbpg8bCvFO9VVCYSgrm?= =?utf-8?q?tHWBkEsMW8IvMO8hHE2xe6c5Bdfq7tAAjnfpKHrnHbZ6cT7Mg2gsrRBXYixYC5LJk?= =?utf-8?q?ktUbLtP8sWrldtSZMrKwxMkKzRCs9XNHmesCrHoMYS5tY4zu81yVUvXNI2P4yacG1?= =?utf-8?q?IHCMOhc3u08SuAspq1wJawp5Yd/CHzAg9koitejOTSGdTztfv+q7yYM2gpVFx7zQL?= =?utf-8?q?muVotm1yQ7Ms+Ce+n9SeyTFtDWXNVAbfQachiAI+2/252fMmmWCx48fK7+vWdc1jG?= =?utf-8?q?9g5J7NbvRA1koqCrA9bozRqJHGZD+putJ8qc16lV5aIZHmowcztry29hV5kE1zK7n?= =?utf-8?q?SisXIMKpWZWVB1trPyT5pgeJGtkYyQejtgw7pADrE/rE+W51LA2sA3ho/l2XpmbET?= =?utf-8?q?Hb93vflS41WWCLAnFq/sw/s9qTSA1dBZhAYFc+jrh/oPdo5uM4aAm//uKbFEDju/D?= =?utf-8?q?7yqmn2TBFpOmb0Jg8XYz0tmtIrmTy0CZLeXE3885qhOPKTLz3yBQju2kbi34Sn350?= =?utf-8?q?nLazYJ0piYUDwYFYaqeryID0Eo0cs3imFVDBV7S9HgVWe3Ou13MMk0vMOnfoJUDYS?= =?utf-8?q?aCSUu27Q4Pta8dMxme+bXZhq8WRRZcPnggLGGe2LWUZU4hFpanBbkPJNt8xV3QiB7?= =?utf-8?q?nEQoesLlaEcRg0kmf/HzKDj+KBd/Q6IKHPu//r+gD+2K5Jezd9hlhtLHy/O3kIwP4?= =?utf-8?q?JiEuEGQylGit/Wed2Q6lT2lFEZRMxfWR9xC3rVFVRYnpdlY+DyRmdJFyMS+eyZpDT?= =?utf-8?q?YYdGChc2TflMhUH6jxxLBc1LXGztgeBordjWFWexh7LkwpPK0LnRH8cFoIXqDgR8y?= =?utf-8?q?uZHhZdLXrITMFI?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: fd941646-53db-40f0-c849-08d925cf61c1 X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jun 2021 14:04:48.0002 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: mmKBsSK5ugnc1ixsx2RFf4v1mvJDYJkKSBbyrM6WArf5wLOiiMIxWZvDE95nKywootYNrg+l+Yqy2xWmhyxNjA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4512 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org An SNP-active guest uses the PVALIDATE instruction to validate or rescind the validation of a guest page’s RMP entry. Upon completion, a return code is stored in EAX and rFLAGS bits are set based on the return code. If the instruction completed successfully, the CF indicates if the content of the RMP were changed or not. See AMD APM Volume 3 for additional details. Signed-off-by: Brijesh Singh --- arch/x86/include/asm/sev.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h index 134a7c9d91b6..1b7a172b832b 100644 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@ -59,6 +59,9 @@ extern void vc_no_ghcb(void); extern void vc_boot_ghcb(void); extern bool handle_vc_boot_ghcb(struct pt_regs *regs); +/* Software defined (when rFlags.CF = 1) */ +#define PVALIDATE_FAIL_NOUPDATE 255 + #ifdef CONFIG_AMD_MEM_ENCRYPT extern struct static_key_false sev_es_enable_key; extern void __sev_es_ist_enter(struct pt_regs *regs); @@ -81,12 +84,29 @@ static __always_inline void sev_es_nmi_complete(void) __sev_es_nmi_complete(); } extern int __init sev_es_efi_map_ghcbs(pgd_t *pgd); +static inline int pvalidate(unsigned long vaddr, bool rmp_psize, bool validate) +{ + bool no_rmpupdate; + int rc; + + asm volatile(".byte 0xF2, 0x0F, 0x01, 0xFF\n\t" + CC_SET(c) + : CC_OUT(c) (no_rmpupdate), "=a"(rc) + : "a"(vaddr), "c"(rmp_psize), "d"(validate) + : "memory", "cc"); + + if (no_rmpupdate) + return PVALIDATE_FAIL_NOUPDATE; + + return rc; +} #else static inline void sev_es_ist_enter(struct pt_regs *regs) { } static inline void sev_es_ist_exit(void) { } static inline int sev_es_setup_ap_jump_table(struct real_mode_header *rmh) { return 0; } static inline void sev_es_nmi_complete(void) { } static inline int sev_es_efi_map_ghcbs(pgd_t *pgd) { return 0; } +static inline int pvalidate(unsigned long vaddr, bool rmp_psize, bool validate) { return 0; } #endif #endif