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Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Andy Lutomirski , Dave Hansen , Sergio Lopez , Peter Gonda , Peter Zijlstra , Srinivas Pandruvada , David Rientjes , Dov Murik , Tobin Feldman-Fitzthum , Borislav Petkov , Michael Roth , Vlastimil Babka , tony.luck@intel.com, npmccallum@redhat.com, brijesh.ksingh@gmail.com, Brijesh Singh Subject: [PATCH Part2 RFC v4 30/40] KVM: X86: Define new RMP check related #NPF error bits Date: Wed, 7 Jul 2021 13:36:06 -0500 Message-Id: <20210707183616.5620-31-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210707183616.5620-1-brijesh.singh@amd.com> References: <20210707183616.5620-1-brijesh.singh@amd.com> X-ClientProxiedBy: SN6PR04CA0078.namprd04.prod.outlook.com (2603:10b6:805:f2::19) To BYAPR12MB2711.namprd12.prod.outlook.com (2603:10b6:a03:63::10) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN6PR04CA0078.namprd04.prod.outlook.com (2603:10b6:805:f2::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4308.20 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Z0cdMLuw0T6bBAbnyyZd3gExyvhWO0L8HhErufAmslxIppHLxkdkEok4lsjw0SVEMsNXNGTRrb0mvZUi+Cw0kYJvfAWQyIuimaAxiMxk8o+ZBwqcfCPdgQ2XinMZfWI8MwAo1jUnjo3GSIqXrY2QAHF9TBco55t4qV020Ah+LEiVl7v//zbwQrdT1w4Hxbz4ThEu0pjIunbAYteng0P0o7Z2REKTukirL/N2AsBiOT+RnC+t6ebr7/9p5Iu40BbNu8mA4F5TaPLyKcOPueZF7kTIDroDXZJHQ89khz7EaY7zImWORk6Ynsjh2xh4cEWmYkKJYDxbrbPOK1yTW/Pe+PRiYKjIFEe4Hy3LhslR4WwUPGmXgrH2qkzHFw2O2uLJJF88RjVn3mkVa7VimvsdRf8RwfO6EApPI+1JmBxcncOHovM/bvqe9UpMghux2amb/jXNECx4Qvf3ymUMZovGZbZFUN228NILcV1koTA3QPVdZyIMuqbsNd39KE2fGrJF14ntomQyeA8rjpMerzBWUkEyf715TcKIoXi1k4+KAbfzdYRtvCQGvnFi4+ZtlrD7423IF1Rwe0bKsNQ0EDyUS73DtDlxFxU8Paz0dulkVVK2qg+6nhQhowwJObxpVC6lthngR+s7Bk+EX7esUrKZMuvqKas7ei1TTxMc5PwYel8C/MmMIsT1TrYTLDN6fgRRWZnNwB1/SIKJI3u78c7sr67H8czqTx8HkUTsUrRrbiiUvJxg1qIjADqNw4rBfJ7/RmcfMHcC6awVFKAvoEJq32yhWF3T527R+r0CQE9O4zwpMudYYKrs9JNj4L8tcMnjnWmdGQZASaJcUuKtiAtzYEiQhCZBPM8AsR9HmrxNbBC5RxEQfxwKW0CLpL5P4EDk8BZIWHjHHHMyOni8jB932mFedCnuA9EqCB/LVCh3P9IW/4aEK5dcNl+0SPKP2r0VurHCbppzV/JO8SyZfDHwh4gBaBPxSDufTzhbWS2M1i+Q7Jv4MTMhGLj5kcGAohA3sjjDYn4hd0DslC9xgWS03DJHmtwAcUqHx0zs2PDWHtF3fdh8bn6F+DzsjJb+dEr0MZiT87T5XSZEe21tw9xtFisZhSX2WyLl7GmvWFLALcybO1zQFZZlgt2uWqz/RBGwWsuhP7C/E28l7Di5739RNBe9AL1Dzm2SB7nUfz/lghCDPDRxt7qKNb8eO4+MORDM6cQi+XnXyd0ew4DtD02PboVI6Gmo0tUlFKIvvA+frsaafXXHvP3OOgajDrM0ljQq4+xWE0n2eBuSkwSo/TvINYIvlGRkN/8C3LHwWPwGsrVdqgoGnKIlzttFOBgZCTlI X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9f6216c3-c8f7-420f-dd66-08d941765fff X-MS-Exchange-CrossTenant-AuthSource: BYAPR12MB2711.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jul 2021 18:38:12.5594 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 2XYg23nNB2yDtQ3DEmDxjNufO2SDOkYMKif3inBzUx/k0PwAynvxEOmBcDaXQBdkDRRYG5uKgArNTiILPVrTSQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4082 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org When SEV-SNP is enabled globally, the hardware places restrictions on all memory accesses based on the RMP entry, whether the hyperviso or a VM, performs the accesses. When hardware encounters an RMP access violation during a guest access, it will cause a #VMEXIT(NPF). See APM2 section 16.36.10 for more details. Signed-off-by: Brijesh Singh --- arch/x86/include/asm/kvm_host.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index cd2e19e1d323..59185b6bc82a 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -239,8 +239,12 @@ enum x86_intercept_stage; #define PFERR_FETCH_BIT 4 #define PFERR_PK_BIT 5 #define PFERR_SGX_BIT 15 +#define PFERR_GUEST_RMP_BIT 31 #define PFERR_GUEST_FINAL_BIT 32 #define PFERR_GUEST_PAGE_BIT 33 +#define PFERR_GUEST_ENC_BIT 34 +#define PFERR_GUEST_SIZEM_BIT 35 +#define PFERR_GUEST_VMPL_BIT 36 #define PFERR_PRESENT_MASK (1U << PFERR_PRESENT_BIT) #define PFERR_WRITE_MASK (1U << PFERR_WRITE_BIT) @@ -251,6 +255,10 @@ enum x86_intercept_stage; #define PFERR_SGX_MASK (1U << PFERR_SGX_BIT) #define PFERR_GUEST_FINAL_MASK (1ULL << PFERR_GUEST_FINAL_BIT) #define PFERR_GUEST_PAGE_MASK (1ULL << PFERR_GUEST_PAGE_BIT) +#define PFERR_GUEST_RMP_MASK (1ULL << PFERR_GUEST_RMP_BIT) +#define PFERR_GUEST_ENC_MASK (1ULL << PFERR_GUEST_ENC_BIT) +#define PFERR_GUEST_SIZEM_MASK (1ULL << PFERR_GUEST_SIZEM_BIT) +#define PFERR_GUEST_VMPL_MASK (1ULL << PFERR_GUEST_VMPL_BIT) #define PFERR_NESTED_GUEST_PAGE (PFERR_GUEST_PAGE_MASK | \ PFERR_WRITE_MASK | \