@@ -86,7 +86,6 @@ struct sa_match_data {
u8 priv;
u8 priv_id;
u32 supported_algos;
- bool skip_engine_control;
};
static struct device *sa_k3_dev;
@@ -2380,7 +2379,6 @@ static struct sa_match_data am64_match_data = {
BIT(SA_ALG_SHA256) |
BIT(SA_ALG_SHA512) |
BIT(SA_ALG_AUTHENC_SHA256_AES),
- .skip_engine_control = true,
};
static const struct of_device_id of_match[] = {
@@ -2398,6 +2396,7 @@ static int sa_ul_probe(struct platform_device *pdev)
struct device_node *node = dev->of_node;
static void __iomem *saul_base;
struct sa_crypto_data *dev_data;
+ u32 status, val;
int ret;
dev_data = devm_kzalloc(dev, sizeof(*dev_data), GFP_KERNEL);
@@ -2434,13 +2433,13 @@ static int sa_ul_probe(struct platform_device *pdev)
spin_lock_init(&dev_data->scid_lock);
- if (!dev_data->match_data->skip_engine_control) {
- u32 val = SA_EEC_ENCSS_EN | SA_EEC_AUTHSS_EN | SA_EEC_CTXCACH_EN |
- SA_EEC_CPPI_PORT_IN_EN | SA_EEC_CPPI_PORT_OUT_EN |
- SA_EEC_TRNG_EN;
-
+ val = SA_EEC_ENCSS_EN | SA_EEC_AUTHSS_EN | SA_EEC_CTXCACH_EN |
+ SA_EEC_CPPI_PORT_IN_EN | SA_EEC_CPPI_PORT_OUT_EN |
+ SA_EEC_TRNG_EN;
+ status = readl_relaxed(saul_base + SA_ENGINE_STATUS);
+ /* Only enable engines if all are not already enabled */
+ if (val & ~status)
writel_relaxed(val, saul_base + SA_ENGINE_ENABLE_CONTROL);
- }
sa_register_algos(dev_data);
@@ -16,6 +16,7 @@
#include <crypto/sha1.h>
#include <crypto/sha2.h>
+#define SA_ENGINE_STATUS 0x0008
#define SA_ENGINE_ENABLE_CONTROL 0x1000
struct sa_tfm_ctx;
There is a engine status register that can be used to check if the different HW crypto engines are enabled. Check that first and then only try to enable the engines if they are not already on. This has a couple benefits. First we don't need to use match_data for this. Second, this driver can now work on HS devices where the engine control registers are read-only and writing causes a firewall exception. Signed-off-by: Andrew Davis <afd@ti.com> --- drivers/crypto/sa2ul.c | 15 +++++++-------- drivers/crypto/sa2ul.h | 1 + 2 files changed, 8 insertions(+), 8 deletions(-)