Message ID | 20230127164040.1047583-4-gatien.chevallier@foss.st.com (mailing list archive) |
---|---|
State | Not Applicable |
Delegated to: | Herbert Xu |
Headers | show |
Series | Introduce STM32 system bus | expand |
On Fri, 27 Jan 2023 17:40:37 +0100 Gatien Chevallier <gatien.chevallier@foss.st.com> wrote: > Document STM32 System Bus. This bus is intended to control firewall > access for the peripherals connected to it. > > Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> > Signed-off-by: Loic PALLARDY <loic.pallardy@st.com> Trivial comment on formatting. > + > +examples: > + - | > + // In this example, the rng1 device refers to etzpc as its domain controller. > + // Same goes for fmc. > + // Access rights are verified before creating devices. > + > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/clock/stm32mp1-clks.h> > + #include <dt-bindings/reset/stm32mp1-resets.h> > + > + etzpc: bus@5c007000 { > + compatible = "st,stm32mp15-sys-bus"; > + reg = <0x5c007000 0x400>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + feature-domain-controller; > + #feature-domain-cells = <1>; > + > + rng1: rng@54003000 { Odd mixture of 4 spacing and 2 spacing in this example. I'd suggest one or the other (slight preference for 4 space indents). > + compatible = "st,stm32-rng"; > + reg = <0x54003000 0x400>; > + clocks = <&rcc RNG1_K>; > + resets = <&rcc RNG1_R>; > + feature-domains = <&etzpc 7>; > + status = "disabled"; > + };
Hello Jonathan, On 1/28/23 16:48, Jonathan Cameron wrote: > On Fri, 27 Jan 2023 17:40:37 +0100 > Gatien Chevallier <gatien.chevallier@foss.st.com> wrote: > >> Document STM32 System Bus. This bus is intended to control firewall >> access for the peripherals connected to it. >> >> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> >> Signed-off-by: Loic PALLARDY <loic.pallardy@st.com> > Trivial comment on formatting. > >> + >> +examples: >> + - | >> + // In this example, the rng1 device refers to etzpc as its domain controller. >> + // Same goes for fmc. >> + // Access rights are verified before creating devices. >> + >> + #include <dt-bindings/interrupt-controller/arm-gic.h> >> + #include <dt-bindings/clock/stm32mp1-clks.h> >> + #include <dt-bindings/reset/stm32mp1-resets.h> >> + >> + etzpc: bus@5c007000 { >> + compatible = "st,stm32mp15-sys-bus"; >> + reg = <0x5c007000 0x400>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges; >> + feature-domain-controller; >> + #feature-domain-cells = <1>; >> + >> + rng1: rng@54003000 { > > Odd mixture of 4 spacing and 2 spacing in this example. > I'd suggest one or the other (slight preference for 4 space indents). > Thank you for spotting this, I'll change to 4 space indents > >> + compatible = "st,stm32-rng"; >> + reg = <0x54003000 0x400>; >> + clocks = <&rcc RNG1_K>; >> + resets = <&rcc RNG1_R>; >> + feature-domains = <&etzpc 7>; >> + status = "disabled"; >> + }; Best regards, Gatien
diff --git a/Documentation/devicetree/bindings/bus/st,sys-bus.yaml b/Documentation/devicetree/bindings/bus/st,sys-bus.yaml new file mode 100644 index 000000000000..c1510784b79b --- /dev/null +++ b/Documentation/devicetree/bindings/bus/st,sys-bus.yaml @@ -0,0 +1,127 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/st,sys-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STM32 System Bus + +description: | + The STM32 System Bus is an internal bus to which some internal peripherals + are connected. STM32 System Bus integrates a firewall controlling access to each + device. This bus prevents non-accessible devices to be probed. + + To see which peripherals are securable, please check the SoC reference manual. + +maintainers: + - Gatien Chevallier <gatien.chevallier@foss.st.com> + +allOf: + - $ref: /schemas/feature-controllers/feature-domain-controller.yaml# + +properties: + compatible: + enum: + - st,stm32mp13-sys-bus + - st,stm32mp15-sys-bus + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + "#feature-domain-cells": + const: 1 + + ranges: true + + feature-domain-controller: true + +patternProperties: + "^.*@[0-9a-f]+$": + description: Devices attached to system bus + type: object + properties: + feature-domains: + $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains + minItems: 1 + maxItems: 3 + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - feature-domain-controller + - "#feature-domain-cells" + - ranges + +additionalProperties: false + +examples: + - | + // In this example, the rng1 device refers to etzpc as its domain controller. + // Same goes for fmc. + // Access rights are verified before creating devices. + + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/stm32mp1-clks.h> + #include <dt-bindings/reset/stm32mp1-resets.h> + + etzpc: bus@5c007000 { + compatible = "st,stm32mp15-sys-bus"; + reg = <0x5c007000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + feature-domain-controller; + #feature-domain-cells = <1>; + + rng1: rng@54003000 { + compatible = "st,stm32-rng"; + reg = <0x54003000 0x400>; + clocks = <&rcc RNG1_K>; + resets = <&rcc RNG1_R>; + feature-domains = <&etzpc 7>; + status = "disabled"; + }; + + fmc: memory-controller@58002000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "st,stm32mp1-fmc2-ebi"; + reg = <0x58002000 0x1000>; + clocks = <&rcc FMC_K>; + resets = <&rcc FMC_R>; + feature-domains = <&etzpc 91>; + status = "disabled"; + + ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ + <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ + <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ + <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ + <4 0 0x80000000 0x10000000>; /* NAND */ + + nand-controller@4,0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp1-fmc2-nfc"; + reg = <4 0x00000000 0x1000>, + <4 0x08010000 0x1000>, + <4 0x08020000 0x1000>, + <4 0x01000000 0x1000>, + <4 0x09010000 0x1000>, + <4 0x09020000 0x1000>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, + <&mdma1 20 0x2 0x12000a08 0x0 0x0>, + <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; + dma-names = "tx", "rx", "ecc"; + status = "disabled"; + }; + }; + };