| Message ID | 20230530160147.9977-1-giovanni.cabiddu@intel.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Herbert Xu |
| Headers | show |
| Series | crypto: qat - update slice mask for 4xxx devices | expand |
On Tue, May 30, 2023 at 05:01:47PM +0100, Giovanni Cabiddu wrote: > From: Karthikeyan Gopal <karthikeyan.gopal@intel.com> > > Update slice mask enum for 4xxx device with BIT(7) to mask SMX fuse. > This change is done to align the slice mask with the hardware fuse > register. > > Signed-off-by: Karthikeyan Gopal <karthikeyan.gopal@intel.com> > Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> > Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> > --- > drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Patch applied. Thanks.
diff --git a/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.h b/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.h index 085e259c245a..e5b314d2b60e 100644 --- a/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.h +++ b/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.h @@ -72,7 +72,7 @@ enum icp_qat_4xxx_slice_mask { ICP_ACCEL_4XXX_MASK_COMPRESS_SLICE = BIT(3), ICP_ACCEL_4XXX_MASK_UCS_SLICE = BIT(4), ICP_ACCEL_4XXX_MASK_EIA3_SLICE = BIT(5), - ICP_ACCEL_4XXX_MASK_SMX_SLICE = BIT(6), + ICP_ACCEL_4XXX_MASK_SMX_SLICE = BIT(7), }; void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data, u32 dev_id);