diff mbox series

[06/30] crypto: artpec6 - stop setting alignmask for ahashes

Message ID 20231022081100.123613-7-ebiggers@kernel.org (mailing list archive)
State Accepted
Delegated to: Herbert Xu
Headers show
Series crypto: reduce ahash API overhead | expand

Commit Message

Eric Biggers Oct. 22, 2023, 8:10 a.m. UTC 
From: Eric Biggers <ebiggers@google.com>

The crypto API's support for alignmasks for ahash algorithms is nearly
useless, as its only effect is to cause the API to align the key and
result buffers.  The drivers that happen to be specifying an alignmask
for ahash rarely actually need it.  When they do, it's easily fixable,
especially considering that these buffers cannot be used for DMA.

In preparation for removing alignmask support from ahash, this patch
makes the artpec6 driver no longer use it.  This driver is unusual in
that it DMAs the digest directly to the result buffer.  This is broken
because the crypto API provides the result buffer as an arbitrary
virtual address, which might not be valid for DMA, even after the crypto
API applies the alignmask.  Maybe the alignmask (which this driver set
only to 3) made this code work in a few more cases than it otherwise
would have.  But even if so, it doesn't make sense for this single
driver that is broken anyway to block removal of the alignmask support.

Signed-off-by: Eric Biggers <ebiggers@google.com>
---
 drivers/crypto/axis/artpec6_crypto.c | 3 ---
 1 file changed, 3 deletions(-)
diff mbox series

Patch

diff --git a/drivers/crypto/axis/artpec6_crypto.c b/drivers/crypto/axis/artpec6_crypto.c
index 8493a45e1bd46..62373a5cd3961 100644
--- a/drivers/crypto/axis/artpec6_crypto.c
+++ b/drivers/crypto/axis/artpec6_crypto.c
@@ -2628,21 +2628,20 @@  static struct ahash_alg hash_algos[] = {
 		.halg.digestsize = SHA1_DIGEST_SIZE,
 		.halg.statesize = sizeof(struct artpec6_hash_export_state),
 		.halg.base = {
 			.cra_name = "sha1",
 			.cra_driver_name = "artpec-sha1",
 			.cra_priority = 300,
 			.cra_flags = CRYPTO_ALG_ASYNC |
 				     CRYPTO_ALG_ALLOCATES_MEMORY,
 			.cra_blocksize = SHA1_BLOCK_SIZE,
 			.cra_ctxsize = sizeof(struct artpec6_hashalg_context),
-			.cra_alignmask = 3,
 			.cra_module = THIS_MODULE,
 			.cra_init = artpec6_crypto_ahash_init,
 			.cra_exit = artpec6_crypto_ahash_exit,
 		}
 	},
 	/* SHA-256 */
 	{
 		.init = artpec6_crypto_sha256_init,
 		.update = artpec6_crypto_hash_update,
 		.final = artpec6_crypto_hash_final,
@@ -2652,21 +2651,20 @@  static struct ahash_alg hash_algos[] = {
 		.halg.digestsize = SHA256_DIGEST_SIZE,
 		.halg.statesize = sizeof(struct artpec6_hash_export_state),
 		.halg.base = {
 			.cra_name = "sha256",
 			.cra_driver_name = "artpec-sha256",
 			.cra_priority = 300,
 			.cra_flags = CRYPTO_ALG_ASYNC |
 				     CRYPTO_ALG_ALLOCATES_MEMORY,
 			.cra_blocksize = SHA256_BLOCK_SIZE,
 			.cra_ctxsize = sizeof(struct artpec6_hashalg_context),
-			.cra_alignmask = 3,
 			.cra_module = THIS_MODULE,
 			.cra_init = artpec6_crypto_ahash_init,
 			.cra_exit = artpec6_crypto_ahash_exit,
 		}
 	},
 	/* HMAC SHA-256 */
 	{
 		.init = artpec6_crypto_hmac_sha256_init,
 		.update = artpec6_crypto_hash_update,
 		.final = artpec6_crypto_hash_final,
@@ -2677,21 +2675,20 @@  static struct ahash_alg hash_algos[] = {
 		.halg.digestsize = SHA256_DIGEST_SIZE,
 		.halg.statesize = sizeof(struct artpec6_hash_export_state),
 		.halg.base = {
 			.cra_name = "hmac(sha256)",
 			.cra_driver_name = "artpec-hmac-sha256",
 			.cra_priority = 300,
 			.cra_flags = CRYPTO_ALG_ASYNC |
 				     CRYPTO_ALG_ALLOCATES_MEMORY,
 			.cra_blocksize = SHA256_BLOCK_SIZE,
 			.cra_ctxsize = sizeof(struct artpec6_hashalg_context),
-			.cra_alignmask = 3,
 			.cra_module = THIS_MODULE,
 			.cra_init = artpec6_crypto_ahash_init_hmac_sha256,
 			.cra_exit = artpec6_crypto_ahash_exit,
 		}
 	},
 };
 
 /* Crypto */
 static struct skcipher_alg crypto_algos[] = {
 	/* AES - ECB */