[01/12] RISC-V: add helper function to read the vector VLEN

Message ID	20231025183644.8735-2-jerry.shih@sifive.com (mailing list archive)
State	Changes Requested
Delegated to:	Herbert Xu
Headers	show Return-Path: <linux-crypto-owner@vger.kernel.org> From: Jerry Shih <jerry.shih@sifive.com> To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, herbert@gondor.apana.org.au, davem@davemloft.net Cc: andy.chiu@sifive.com, greentime.hu@sifive.com, conor.dooley@microchip.com, guoren@kernel.org, bjorn@rivosinc.com, heiko@sntech.de, ebiggers@kernel.org, ardb@kernel.org, phoebe.chen@sifive.com, hongrong.hsu@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org Subject: [PATCH 01/12] RISC-V: add helper function to read the vector VLEN Date: Thu, 26 Oct 2023 02:36:33 +0800 Message-Id: <20231025183644.8735-2-jerry.shih@sifive.com> In-Reply-To: <20231025183644.8735-1-jerry.shih@sifive.com> References: <20231025183644.8735-1-jerry.shih@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	RISC-V: provide some accelerated cryptography implementations using vector extensions \| expand [00/12] RISC-V: provide some accelerated cryptography implementations using vector extensions [01/12] RISC-V: add helper function to read the vector VLEN [02/12] RISC-V: hook new crypto subdir into build-system [03/12] RISC-V: crypto: add OpenSSL perl module for vector instructions [04/12] RISC-V: crypto: add Zvkned accelerated AES implementation [05/12] crypto: scatterwalk - Add scatterwalk_next() to get the next scatterlist in scatter_walk [06/12] RISC-V: crypto: add accelerated AES-CBC/CTR/ECB/XTS implementations [07/12] RISC-V: crypto: add Zvkg accelerated GCM GHASH implementation [08/12] RISC-V: crypto: add Zvknha/b accelerated SHA224/256 implementations [09/12] RISC-V: crypto: add Zvknhb accelerated SHA384/512 implementations [10/12] RISC-V: crypto: add Zvksed accelerated SM4 implementation [11/12] RISC-V: crypto: add Zvksh accelerated SM3 implementation [12/12] RISC-V: crypto: add Zvkb accelerated ChaCha20 implementation

Message ID

20231025183644.8735-2-jerry.shih@sifive.com (mailing list archive)

State

Changes Requested

Delegated to:

Herbert Xu

Headers

From: Jerry Shih <jerry.shih@sifive.com>
To: paul.walmsley@sifive.com, palmer@dabbelt.com,
        aou@eecs.berkeley.edu, herbert@gondor.apana.org.au,
        davem@davemloft.net
Cc: andy.chiu@sifive.com, greentime.hu@sifive.com,
        conor.dooley@microchip.com, guoren@kernel.org, bjorn@rivosinc.com,
        heiko@sntech.de, ebiggers@kernel.org, ardb@kernel.org,
        phoebe.chen@sifive.com, hongrong.hsu@sifive.com,
        linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
        linux-crypto@vger.kernel.org
Subject: [PATCH 01/12] RISC-V: add helper function to read the vector VLEN
Date: Thu, 26 Oct 2023 02:36:33 +0800
Message-Id: <20231025183644.8735-2-jerry.shih@sifive.com>
In-Reply-To: <20231025183644.8735-1-jerry.shih@sifive.com>
References: <20231025183644.8735-1-jerry.shih@sifive.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: bulk

Series

RISC-V: provide some accelerated cryptography implementations using vector extensions | expand

Commit Message

Jerry Shih Oct. 25, 2023, 6:36 p.m. UTC

From: Heiko Stuebner <heiko.stuebner@vrull.eu>

VLEN describes the length of each vector register and some instructions
need specific minimal VLENs to work correctly.

The vector code already includes a variable riscv_v_vsize that contains
the value of "32 vector registers with vlenb length" that gets filled
during boot. vlenb is the value contained in the CSR_VLENB register and
the value represents "VLEN / 8".

So add riscv_vector_vlen() to return the actual VLEN value for in-kernel
users when they need to check the available VLEN.

Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Signed-off-by: Jerry Shih <jerry.shih@sifive.com>
---
 arch/riscv/include/asm/vector.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
index 9fb2dea66abd..1fd3e5510b64 100644
--- a/arch/riscv/include/asm/vector.h
+++ b/arch/riscv/include/asm/vector.h
@@ -244,4 +244,15 @@  void kernel_vector_allow_preemption(void);
 #define kernel_vector_allow_preemption()	do {} while (0)
 #endif
 
+/*
+ * Return the implementation's vlen value.
+ *
+ * riscv_v_vsize contains the value of "32 vector registers with vlenb length"
+ * so rebuild the vlen value in bits from it.
+ */
+static inline int riscv_vector_vlen(void)
+{
+	return riscv_v_vsize / 32 * 8;
+}
+
 #endif /* ! __ASM_RISCV_VECTOR_H */

[01/12] RISC-V: add helper function to read the vector VLEN

Commit Message

Patch