| Message ID | 20240329225835.400662-6-michael.roth@amd.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Delegated to: | Herbert Xu |
| Headers | show |
| Series | Add AMD Secure Nested Paging (SEV-SNP) Hypervisor Support | expand |
On 3/29/24 23:58, Michael Roth wrote: > From: Brijesh Singh <brijesh.singh@amd.com> > > When SEV-SNP is enabled globally, the hardware places restrictions on > all memory accesses based on the RMP entry, whether the hypervisor or a > VM, performs the accesses. When hardware encounters an RMP access > violation during a guest access, it will cause a #VMEXIT(NPF) with a > number of additional bits set to indicate the reasons for the #NPF. > Define those here. > > See APM2 section 16.36.10 for more details. > > Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> > Signed-off-by: Ashish Kalra <ashish.kalra@amd.com> > [mdr: add some additional details to commit message] > Signed-off-by: Michael Roth <michael.roth@amd.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> One nit below. > --- > arch/x86/include/asm/kvm_host.h | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h > index 90dc0ae9311a..a3f8eba8d8b6 100644 > --- a/arch/x86/include/asm/kvm_host.h > +++ b/arch/x86/include/asm/kvm_host.h > @@ -262,9 +262,12 @@ enum x86_intercept_stage; > #define PFERR_FETCH_BIT 4 > #define PFERR_PK_BIT 5 > #define PFERR_SGX_BIT 15 > +#define PFERR_GUEST_RMP_BIT 31 > #define PFERR_GUEST_FINAL_BIT 32 > #define PFERR_GUEST_PAGE_BIT 33 > #define PFERR_GUEST_ENC_BIT 34 > +#define PFERR_GUEST_SIZEM_BIT 35 > +#define PFERR_GUEST_VMPL_BIT 36 > #define PFERR_IMPLICIT_ACCESS_BIT 48 > > #define PFERR_PRESENT_MASK BIT(PFERR_PRESENT_BIT) > @@ -277,7 +280,10 @@ enum x86_intercept_stage; > #define PFERR_GUEST_FINAL_MASK BIT_ULL(PFERR_GUEST_FINAL_BIT) > #define PFERR_GUEST_PAGE_MASK BIT_ULL(PFERR_GUEST_PAGE_BIT) > #define PFERR_GUEST_ENC_MASK BIT_ULL(PFERR_GUEST_ENC_BIT) > +#define PFERR_GUEST_RMP_MASK BIT_ULL(PFERR_GUEST_RMP_BIT) > +#define PFERR_GUEST_SIZEM_MASK BIT_ULL(PFERR_GUEST_SIZEM_BIT) > #define PFERR_IMPLICIT_ACCESS BIT_ULL(PFERR_IMPLICIT_ACCESS_BIT) > +#define PFERR_GUEST_VMPL_MASK BIT_ULL(PFERR_GUEST_VMPL_BIT) Should be kept in either bit order or perhaps alphabetical order (probably bit is better). Paolo > #define PFERR_NESTED_GUEST_PAGE (PFERR_GUEST_PAGE_MASK | \ > PFERR_WRITE_MASK | \
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 90dc0ae9311a..a3f8eba8d8b6 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -262,9 +262,12 @@ enum x86_intercept_stage; #define PFERR_FETCH_BIT 4 #define PFERR_PK_BIT 5 #define PFERR_SGX_BIT 15 +#define PFERR_GUEST_RMP_BIT 31 #define PFERR_GUEST_FINAL_BIT 32 #define PFERR_GUEST_PAGE_BIT 33 #define PFERR_GUEST_ENC_BIT 34 +#define PFERR_GUEST_SIZEM_BIT 35 +#define PFERR_GUEST_VMPL_BIT 36 #define PFERR_IMPLICIT_ACCESS_BIT 48 #define PFERR_PRESENT_MASK BIT(PFERR_PRESENT_BIT) @@ -277,7 +280,10 @@ enum x86_intercept_stage; #define PFERR_GUEST_FINAL_MASK BIT_ULL(PFERR_GUEST_FINAL_BIT) #define PFERR_GUEST_PAGE_MASK BIT_ULL(PFERR_GUEST_PAGE_BIT) #define PFERR_GUEST_ENC_MASK BIT_ULL(PFERR_GUEST_ENC_BIT) +#define PFERR_GUEST_RMP_MASK BIT_ULL(PFERR_GUEST_RMP_BIT) +#define PFERR_GUEST_SIZEM_MASK BIT_ULL(PFERR_GUEST_SIZEM_BIT) #define PFERR_IMPLICIT_ACCESS BIT_ULL(PFERR_IMPLICIT_ACCESS_BIT) +#define PFERR_GUEST_VMPL_MASK BIT_ULL(PFERR_GUEST_VMPL_BIT) #define PFERR_NESTED_GUEST_PAGE (PFERR_GUEST_PAGE_MASK | \ PFERR_WRITE_MASK | \