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V" , Alexey Kardashevskiy Subject: [RFC PATCH v2 02/22] PCI/IDE: Fixes to make it work on AMD SNP-SEV Date: Tue, 18 Feb 2025 22:09:49 +1100 Message-ID: <20250218111017.491719-3-aik@amd.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250218111017.491719-1-aik@amd.com> References: <20250218111017.491719-1-aik@amd.com> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B075:EE_|CY8PR12MB7436:EE_ X-MS-Office365-Filtering-Correlation-Id: c77afa49-27fb-47d1-27a7-08dd500cf7b4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: TYz8Q7wpSnNrDA06/9J78ZVY8aO4FD99MnslBNCrpNLWuYCoi8kNaZDExjkabiaMQdz/0/P+3V2QdoCAj+Ttf/+m0Y0sBJbZzUp7z69x7U8GiY4UB6Qf1l2O40E+nrxoCfixJRE6kDHvBLWgi0KRtOqs9BbhIQwr1VXxtY6x1uIS19o2FZ+7Rjqndf8CASG9lsAS6ad0H4QImyN4a6SDkitkeNqemiFHIi006s/T3xVhNAnxmD4bNc4jzmbq7QVrJOql247Z0qFc7u2GeFlNULp2Gnc2xExplct5306qlm95IW7yn7pRPqHpYNo+7KsqrBEGmTY95YjtLixpnjtkxtCOmwyM2voI3Y0dVMegGSXOyWLWubTXBdOMWtD4GLGbM9T7Apvv64KQRYsfpKcQGSBoHACSlcvqI9J76xwzaAcAUxwhdFabR4Fq9SRkNLcmVCksou/F5Mr919Rup70Y1vn8awiYZnK/duq4Eihbufyhua/hP0rZb5iHW89+lL0htj3KmsHgxwQ6RGzB4c2ZWBz8imk5nVrwImdSEkCmreQn4WBDk+Gde9MEYhI7erPkjK5NyPrPqVVO48/H24BVD+Nau1GthnYuipnl5AiBglKaHol8v0z6awonsxzyc7dMS+3gcqQ4sROuVFQLFJGmPmxwijifBHGflf6FmADm0BxZ4RU+4cVoePKbyHf8lKovzgGNaROHGDVtoe902MS2sp9Iqd2bo9oghMlQrrL1wDh4qr14wbAACXCQLXU0Xv4bgp7EZvu2UuEc1Ys/rwJ+JotWIlWSaxWVObc6y4Ixm5d9oJQGjCPdlGrmu41DhI8tOFt64k/etRYYOdFbTmBmIXkbBVtTlgwfn+fvIBBiYm2UFszPMEzntAfDaisZ/mZ12l3H4FnA5NZ/o6PHq57KCYAwRr7LbgZSnmkU9ljicsZPQzSZqHpLg/Yy0wozMnTYC4v1q118UaO9RRu97qm9OEdmVGuw6aVKj4BfmSlLTlXe/haQbSy6ggBe0EmJGU3gKpBdV+XQf1ME9b43ftttRhuh6qdpjwrEcowF8dtDXQjgdGgAWXz5mTNOjZ4SZcb43FDoYMUZqyZr+JtFhvvZXXBZY6+JarEVvEHPnd+m+e+rQen2Yaga+yiywIc/jMLN1N12gJ2duYx74008RFRWRbKTjTay9xN68hR/ZfXVkIF4mEavMNBEFlFIqpwcaVd+NQ9/pv3wfkGocOLketW8Uro8tak6skfG9jm+lmhs1HCIRmBExR1MIalEx+c1ab1i7FEcNdyD6+UQfWaeWL1JEnjMcSal1JQUNKXDe9aQI5X2QufUNa5F9g8YEr8n3prevlUdMoiVB4XYtJiCHVymGbWZP/DV2RTXrTsPpyVAefR5br4iMKkjoRAK73T5dpN5AxuNINJAWO2bIpJpOhDFo+iy/kprQCaxjgU+WMU4CctUwa9UPwtqVJxtHtZewyKGkeZnR7wBEhfwulY7TyqtBShwYI9XWBwpa0ic0lpIDCY= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:sk;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(376014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Feb 2025 11:11:18.1618 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c77afa49-27fb-47d1-27a7-08dd500cf7b4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B075.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7436 The IDE proposed patches do setup of endpoints while they should focus on root port. These are workarounds better be discussed in "[PATCH 00/11] PCI/TSM: Core infrastructure for PCI device security (TDISP)" Signed-off-by: Alexey Kardashevskiy --- include/linux/pci-ide.h | 19 +++-- include/uapi/linux/pci_regs.h | 4 +- drivers/pci/ide.c | 76 ++++++++++++++++---- 3 files changed, 78 insertions(+), 21 deletions(-) diff --git a/include/linux/pci-ide.h b/include/linux/pci-ide.h index 24e08a413645..f784fb16cc88 100644 --- a/include/linux/pci-ide.h +++ b/include/linux/pci-ide.h @@ -8,26 +8,33 @@ #include +enum pci_ide_flags { + PCI_IDE_SETUP_ROOT_PORT = BIT(0), + PCI_IDE_SETUP_ROOT_PORT_MEM = BIT(1), +}; + struct pci_ide { int domain; u16 devid_start; u16 devid_end; + u16 rpid_start; + u16 rpid_end; int stream_id; const char *name; int nr_mem; struct range mem[16]; + unsigned int dev_sel_ctl; + unsigned int rootport_sel_ctl; + enum pci_ide_flags flags; }; void pci_ide_stream_probe(struct pci_dev *pdev, struct pci_ide *ide); -enum pci_ide_flags { - PCI_IDE_SETUP_ROOT_PORT = BIT(0), -}; - int pci_ide_stream_setup(struct pci_dev *pdev, struct pci_ide *ide, enum pci_ide_flags flags); -void pci_ide_stream_teardown(struct pci_dev *pdev, struct pci_ide *ide, - enum pci_ide_flags flags); +void pci_ide_stream_teardown(struct pci_dev *pdev, struct pci_ide *ide); void pci_ide_enable_stream(struct pci_dev *pdev, struct pci_ide *ide); void pci_ide_disable_stream(struct pci_dev *pdev, struct pci_ide *ide); +int pci_ide_stream_state(struct pci_dev *pdev, struct pci_ide *ide, u32 *status, u32 *rpstatus); + #endif /* __PCI_IDE_H__ */ diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 498c6b298186..15bd8e2b3cf5 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1293,9 +1293,9 @@ /* Selective IDE Address Association Register Block, up to PCI_IDE_SEL_CAP_ASSOC_NUM */ #define PCI_IDE_SEL_ADDR_1(x) (20 + (x) * 12) #define PCI_IDE_SEL_ADDR_1_VALID 0x1 -#define PCI_IDE_SEL_ADDR_1_BASE_LOW_MASK 0x000fff0 +#define PCI_IDE_SEL_ADDR_1_BASE_LOW_MASK 0x000fff00 #define PCI_IDE_SEL_ADDR_1_BASE_LOW_SHIFT 20 -#define PCI_IDE_SEL_ADDR_1_LIMIT_LOW_MASK 0xfff0000 +#define PCI_IDE_SEL_ADDR_1_LIMIT_LOW_MASK 0xfff00000 #define PCI_IDE_SEL_ADDR_1_LIMIT_LOW_SHIFT 20 /* IDE Address Association Register 2 is "Memory Limit Upper" */ /* IDE Address Association Register 3 is "Memory Base Upper" */ diff --git a/drivers/pci/ide.c b/drivers/pci/ide.c index 500b63e149cf..3c53b27f8447 100644 --- a/drivers/pci/ide.c +++ b/drivers/pci/ide.c @@ -50,10 +50,10 @@ void pci_ide_init(struct pci_dev *pdev) else sel_ide_cap = ide_cap + PCI_IDE_LINK_STREAM; - for (int i = 0; i < PCI_IDE_CAP_SELECTIVE_STREAMS_NUM(val); i++) { + for (int i = 0; i < PCI_IDE_CAP_SELECTIVE_STREAMS_NUM(val) + 1; i++) { if (i == 0) { pci_read_config_dword(pdev, sel_ide_cap, &val); - nr_ide_mem = PCI_IDE_SEL_CAP_ASSOC_NUM(val); + nr_ide_mem = PCI_IDE_SEL_CAP_ASSOC_NUM(val) + 1; } else { int offset = sel_ide_offset(sel_ide_cap, i, nr_ide_mem); @@ -118,7 +118,7 @@ void pci_set_nr_ide_streams(struct pci_host_bridge *hb, int nr) hb->nr_ide_streams = nr; sysfs_update_group(&hb->dev.kobj, &pci_ide_attr_group); } -EXPORT_SYMBOL_NS_GPL(pci_set_nr_ide_streams, PCI_IDE); +EXPORT_SYMBOL_NS_GPL(pci_set_nr_ide_streams, "PCI_IDE"); void pci_init_host_bridge_ide(struct pci_host_bridge *hb) { @@ -148,6 +148,10 @@ void pci_ide_stream_probe(struct pci_dev *pdev, struct pci_ide *ide) else ide->devid_end = ide->devid_start; + /* Enable everything into the rootport by default */ + ide->rpid_start = 0; + ide->rpid_end = 0xffff; + /* TODO: address association probing... */ } EXPORT_SYMBOL_GPL(pci_ide_stream_probe); @@ -160,7 +164,7 @@ static void __pci_ide_stream_teardown(struct pci_dev *pdev, struct pci_ide *ide) pdev->nr_ide_mem); pci_write_config_dword(pdev, pos + PCI_IDE_SEL_CTL, 0); - for (int i = ide->nr_mem - 1; i >= 0; i--) { + for (int i = min(ide->nr_mem, pdev->nr_ide_mem) - 1; i >= 0; i--) { pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_3(i), 0); pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_2(i), 0); pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_1(i), 0); @@ -169,7 +173,7 @@ static void __pci_ide_stream_teardown(struct pci_dev *pdev, struct pci_ide *ide) pci_write_config_dword(pdev, pos + PCI_IDE_SEL_RID_1, 0); } -static void __pci_ide_stream_setup(struct pci_dev *pdev, struct pci_ide *ide) +static int __pci_ide_stream_setup(struct pci_dev *pdev, struct pci_ide *ide, bool mem, bool rp) { int pos; u32 val; @@ -177,14 +181,20 @@ static void __pci_ide_stream_setup(struct pci_dev *pdev, struct pci_ide *ide) pos = sel_ide_offset(pdev->sel_ide_cap, ide->stream_id, pdev->nr_ide_mem); - val = FIELD_PREP(PCI_IDE_SEL_RID_1_LIMIT_MASK, ide->devid_end); + val = FIELD_PREP(PCI_IDE_SEL_RID_1_LIMIT_MASK, rp ? ide->rpid_end : ide->devid_end); pci_write_config_dword(pdev, pos + PCI_IDE_SEL_RID_1, val); val = FIELD_PREP(PCI_IDE_SEL_RID_2_VALID, 1) | - FIELD_PREP(PCI_IDE_SEL_RID_2_BASE_MASK, ide->devid_start) | + FIELD_PREP(PCI_IDE_SEL_RID_2_BASE_MASK, rp ? ide->rpid_start : ide->devid_start) | FIELD_PREP(PCI_IDE_SEL_RID_2_SEG_MASK, ide->domain); pci_write_config_dword(pdev, pos + PCI_IDE_SEL_RID_2, val); + if (!mem) + return 0; + + if (ide->nr_mem > pdev->nr_ide_mem) + return -EINVAL; + for (int i = 0; i < ide->nr_mem; i++) { val = FIELD_PREP(PCI_IDE_SEL_ADDR_1_VALID, 1) | FIELD_PREP(PCI_IDE_SEL_ADDR_1_BASE_LOW_MASK, @@ -201,6 +211,8 @@ static void __pci_ide_stream_setup(struct pci_dev *pdev, struct pci_ide *ide) val = upper_32_bits(ide->mem[i].start); pci_write_config_dword(pdev, pos + PCI_IDE_SEL_ADDR_3(i), val); } + + return 0; } /* @@ -248,10 +260,14 @@ int pci_ide_stream_setup(struct pci_dev *pdev, struct pci_ide *ide, goto err; } - __pci_ide_stream_setup(pdev, ide); - if (flags & PCI_IDE_SETUP_ROOT_PORT) - __pci_ide_stream_setup(rp, ide); + rc = __pci_ide_stream_setup(pdev, ide, true, false); + if (!rc && (flags & PCI_IDE_SETUP_ROOT_PORT)) + rc = __pci_ide_stream_setup(rp, ide, !!(flags & PCI_IDE_SETUP_ROOT_PORT_MEM), true); + + if (rc) + goto err; + ide->flags = flags; return 0; err: for (; mem >= 0; mem--) @@ -268,6 +284,7 @@ EXPORT_SYMBOL_GPL(pci_ide_stream_setup); void pci_ide_enable_stream(struct pci_dev *pdev, struct pci_ide *ide) { + struct pci_dev *rp = pcie_find_root_port(pdev); int pos; u32 val; @@ -276,14 +293,27 @@ void pci_ide_enable_stream(struct pci_dev *pdev, struct pci_ide *ide) val = FIELD_PREP(PCI_IDE_SEL_CTL_ID_MASK, ide->stream_id) | FIELD_PREP(PCI_IDE_SEL_CTL_DEFAULT, 1); + val |= FIELD_PREP(PCI_IDE_SEL_CTL_EN, 1); + /* there is rootport and pdev is not it */ + if (rp && rp != pdev) + val |= ide->dev_sel_ctl; + else + val |= ide->rootport_sel_ctl; pci_write_config_dword(pdev, pos + PCI_IDE_SEL_CTL, val); + + if (ide->flags & PCI_IDE_SETUP_ROOT_PORT && rp && rp != pdev) + pci_ide_enable_stream(rp, ide); } EXPORT_SYMBOL_GPL(pci_ide_enable_stream); void pci_ide_disable_stream(struct pci_dev *pdev, struct pci_ide *ide) { + struct pci_dev *rp = pcie_find_root_port(pdev); int pos; + if (ide->flags & PCI_IDE_SETUP_ROOT_PORT && rp && rp != pdev) + pci_ide_disable_stream(rp, ide); + pos = sel_ide_offset(pdev->sel_ide_cap, ide->stream_id, pdev->nr_ide_mem); @@ -291,14 +321,13 @@ void pci_ide_disable_stream(struct pci_dev *pdev, struct pci_ide *ide) } EXPORT_SYMBOL_GPL(pci_ide_disable_stream); -void pci_ide_stream_teardown(struct pci_dev *pdev, struct pci_ide *ide, - enum pci_ide_flags flags) +void pci_ide_stream_teardown(struct pci_dev *pdev, struct pci_ide *ide) { struct pci_host_bridge *hb = pci_find_host_bridge(pdev->bus); struct pci_dev *rp = pcie_find_root_port(pdev); __pci_ide_stream_teardown(pdev, ide); - if (flags & PCI_IDE_SETUP_ROOT_PORT) + if (ide->flags & PCI_IDE_SETUP_ROOT_PORT) __pci_ide_stream_teardown(rp, ide); for (int i = ide->nr_mem - 1; i >= 0; i--) @@ -309,3 +338,24 @@ void pci_ide_stream_teardown(struct pci_dev *pdev, struct pci_ide *ide, clear_bit_unlock(ide->stream_id, hb->ide_stream_ids); } EXPORT_SYMBOL_GPL(pci_ide_stream_teardown); + +static int __pci_ide_stream_state(struct pci_dev *pdev, struct pci_ide *ide, u32 *status) +{ + int pos = sel_ide_offset(pdev->sel_ide_cap, ide->stream_id, + pdev->nr_ide_mem); + + return pci_read_config_dword(pdev, pos + PCI_IDE_SEL_STS, status); +} + +int pci_ide_stream_state(struct pci_dev *pdev, struct pci_ide *ide, u32 *status, u32 *rpstatus) +{ + int ret = __pci_ide_stream_state(pdev, ide, status); + + if (!ret && ide->flags & PCI_IDE_SETUP_ROOT_PORT) { + struct pci_dev *rp = pcie_find_root_port(pdev); + + ret = __pci_ide_stream_state(rp, ide, rpstatus); + } + return ret; +} +EXPORT_SYMBOL_GPL(pci_ide_stream_state);