From patchwork Mon Jul 6 21:14:39 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Hilman X-Patchwork-Id: 34321 Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n66LIPYn016757 for ; Mon, 6 Jul 2009 21:18:26 GMT Received: from dlep36.itg.ti.com ([157.170.170.91]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id n66LGbef013458; Mon, 6 Jul 2009 16:16:42 -0500 Received: from linux.omap.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id n66LGbp1015370; Mon, 6 Jul 2009 16:16:37 -0500 (CDT) Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id 8E7928062A; Mon, 6 Jul 2009 16:16:36 -0500 (CDT) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dflp52.itg.ti.com (dflp52.itg.ti.com [128.247.22.96]) by linux.omap.com (Postfix) with ESMTP id 4890B80628 for ; Mon, 6 Jul 2009 16:16:02 -0500 (CDT) Received: from red.ext.ti.com (localhost [127.0.0.1]) by dflp52.itg.ti.com (8.13.7/8.13.7) with ESMTP id n66LG2sU025464 for ; Mon, 6 Jul 2009 16:16:02 -0500 (CDT) Received: from mail179-wa4-R.bigfish.com (mail-wa4.bigfish.com [216.32.181.114]) by red.ext.ti.com (8.13.7/8.13.7) with ESMTP id n66LFug6009598 for ; Mon, 6 Jul 2009 16:16:01 -0500 Received: from mail179-wa4 (localhost.localdomain [127.0.0.1]) by mail179-wa4-R.bigfish.com (Postfix) with ESMTP id 981A71E8081 for ; Mon, 6 Jul 2009 21:15:56 +0000 (UTC) X-SpamScore: 0 X-BigFish: vps0(zzzz1202hzzz2dh63h) X-Spam-TCS-SCL: 2:0 X-MS-Exchange-Organization-Antispam-Report: OrigIP: 209.85.222.185; Service: EHS Received: by mail179-wa4 (MessageSwitch) id 1246914953450376_1898; Mon, 6 Jul 2009 21:15:53 +0000 (UCT) Received: from mail-pz0-f185.google.com (mail-pz0-f185.google.com [209.85.222.185]) by mail179-wa4.bigfish.com (Postfix) with ESMTP id 5B594D80058 for ; Mon, 6 Jul 2009 21:15:53 +0000 (UTC) Received: by mail-pz0-f185.google.com with SMTP id 15so474410pzk.4 for ; Mon, 06 Jul 2009 14:15:53 -0700 (PDT) Received: by 10.114.173.8 with SMTP id v8mr8301792wae.169.1246914952574; Mon, 06 Jul 2009 14:15:52 -0700 (PDT) Received: from localhost ([216.254.16.51]) by mx.google.com with ESMTPS id m28sm11947942waf.2.2009.07.06.14.15.49 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 06 Jul 2009 14:15:51 -0700 (PDT) From: Kevin Hilman To: linux-arm-kernel@lists.arm.linux.org.uk Date: Mon, 6 Jul 2009 14:14:39 -0700 Message-Id: <1246914900-9034-6-git-send-email-khilman@deeprootsystems.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1246914900-9034-5-git-send-email-khilman@deeprootsystems.com> References: <1246914900-9034-1-git-send-email-khilman@deeprootsystems.com> <1246914900-9034-2-git-send-email-khilman@deeprootsystems.com> <1246914900-9034-3-git-send-email-khilman@deeprootsystems.com> <1246914900-9034-4-git-send-email-khilman@deeprootsystems.com> <1246914900-9034-5-git-send-email-khilman@deeprootsystems.com> Cc: davinci-linux-open-source@linux.davincidsp.com, Naresh Medisetty Subject: [PATCH 05/26] davinci: EDMA: add support for dm646x X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.4 Precedence: list List-Id: davinci-linux-open-source.linux.davincidsp.com List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: davinci-linux-open-source-bounces@linux.davincidsp.com Errors-To: davinci-linux-open-source-bounces@linux.davincidsp.com From: Sudhakar Rajashekhara Enables module clock for DM646x EDMA channel controller and transfer controller. Channel mapping logic is introduced in dm646x EDMA. This implies that there is no fixed association for a channel number to a parameter entry number. In other words, using the DMA channel mapping registers (DCHMAPn), a PaRAM entry can be mapped to any channel. While in the case of dm644x and dm355 there is a fixed mapping between the EDMA channel and Param entry number. Signed-off-by: Naresh Medisetty Signed-off-by: Sudhakar Rajashekhara Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/dm646x.c | 40 ++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-davinci/dma.c | 25 +++++++++++++++++++++++++ 2 files changed, 65 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index d32d2b8..5326edf 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -162,6 +162,41 @@ static struct clk arm_clk = { .flags = ALWAYS_ENABLED, }; +static struct clk edma_cc_clk = { + .name = "edma_cc", + .parent = &pll1_sysclk2, + .lpsc = DM646X_LPSC_TPCC, + .flags = ALWAYS_ENABLED, +}; + +static struct clk edma_tc0_clk = { + .name = "edma_tc0", + .parent = &pll1_sysclk2, + .lpsc = DM646X_LPSC_TPTC0, + .flags = ALWAYS_ENABLED, +}; + +static struct clk edma_tc1_clk = { + .name = "edma_tc1", + .parent = &pll1_sysclk2, + .lpsc = DM646X_LPSC_TPTC1, + .flags = ALWAYS_ENABLED, +}; + +static struct clk edma_tc2_clk = { + .name = "edma_tc2", + .parent = &pll1_sysclk2, + .lpsc = DM646X_LPSC_TPTC2, + .flags = ALWAYS_ENABLED, +}; + +static struct clk edma_tc3_clk = { + .name = "edma_tc3", + .parent = &pll1_sysclk2, + .lpsc = DM646X_LPSC_TPTC3, + .flags = ALWAYS_ENABLED, +}; + static struct clk uart0_clk = { .name = "uart0", .parent = &aux_clkin, @@ -269,6 +304,11 @@ struct davinci_clk dm646x_clks[] = { CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), CLK(NULL, "dsp", &dsp_clk), CLK(NULL, "arm", &arm_clk), + CLK(NULL, "edma_cc", &edma_cc_clk), + CLK(NULL, "edma_tc0", &edma_tc0_clk), + CLK(NULL, "edma_tc1", &edma_tc1_clk), + CLK(NULL, "edma_tc2", &edma_tc2_clk), + CLK(NULL, "edma_tc3", &edma_tc3_clk), CLK(NULL, "uart0", &uart0_clk), CLK(NULL, "uart1", &uart1_clk), CLK(NULL, "uart2", &uart2_clk), diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c index 50ac74f..1c60de6 100644 --- a/arch/arm/mach-davinci/dma.c +++ b/arch/arm/mach-davinci/dma.c @@ -104,6 +104,9 @@ #define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5)) +#define EDMA_DCHMAP 0x0100 /* 64 registers */ +#define CHMAP_EXIST BIT(24) + #define EDMA_MAX_DMACH 64 #define EDMA_MAX_PARAMENTRY 512 #define EDMA_MAX_CC 2 @@ -287,6 +290,24 @@ static void __init assign_priority_to_queue(unsigned ctlr, int queue_no, ((priority & 0x7) << bit)); } +/** + * map_dmach_param - Maps channel number to param entry number + * + * This maps the dma channel number to param entry numberter. In + * other words using the DMA channel mapping registers a param entry + * can be mapped to any channel + * + * Callers are responsible for ensuring the channel mapping logic is + * included in that particular EDMA variant (Eg : dm646x) + * + */ +static void __init map_dmach_param(unsigned ctlr) +{ + int i; + for (i = 0; i < EDMA_MAX_DMACH; i++) + edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5)); +} + static inline void setup_dma_interrupt(unsigned lch, void (*callback)(unsigned channel, u16 ch_status, void *data), @@ -1287,6 +1308,10 @@ static int __init edma_probe(struct platform_device *pdev) assign_priority_to_queue(pdev->id, queue_priority_mapping[i][0], queue_priority_mapping[i][1]); + /* Map the channel to param entry if channel mapping logic exist */ + if (edma_read(pdev->id, EDMA_CCCFG) & CHMAP_EXIST) + map_dmach_param(pdev->id); + for (i = 0; i < info->n_region; i++) { edma_write_array2(pdev->id, EDMA_DRAE, i, 0, 0x0); edma_write_array2(pdev->id, EDMA_DRAE, i, 1, 0x0);