From patchwork Tue Nov 10 18:01:30 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Daniel_Gl=C3=B6ckner?= X-Patchwork-Id: 59118 Received: from comal.ext.ti.com (comal.ext.ti.com [198.47.26.152]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id nAAI3bLn004601 for ; Tue, 10 Nov 2009 18:03:38 GMT Received: from dlep33.itg.ti.com ([157.170.170.112]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id nAAI1lMG015330 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 10 Nov 2009 12:01:47 -0600 Received: from linux.omap.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id nAAI1kr1024590; Tue, 10 Nov 2009 12:01:46 -0600 (CST) Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id 7E8D780627; Tue, 10 Nov 2009 12:01:46 -0600 (CST) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dflp53.itg.ti.com (dflp53.itg.ti.com [128.247.5.6]) by linux.omap.com (Postfix) with ESMTP id 444A180626 for ; Tue, 10 Nov 2009 12:01:44 -0600 (CST) Received: from white.ext.ti.com (localhost [127.0.0.1]) by dflp53.itg.ti.com (8.13.8/8.13.8) with ESMTP id nAAI1gYW022952 for ; Tue, 10 Nov 2009 12:01:42 -0600 (CST) Received: from mail133-tx2-R.bigfish.com (mail-tx2.bigfish.com [65.55.88.113]) by white.ext.ti.com (8.13.7/8.13.7) with ESMTP id nAAI1ceT002443 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=FAIL) for ; Tue, 10 Nov 2009 12:01:39 -0600 Received: from mail133-tx2 (localhost.localdomain [127.0.0.1]) by mail133-tx2-R.bigfish.com (Postfix) with ESMTP id A5E9214F81BC for ; Tue, 10 Nov 2009 18:01:37 +0000 (UTC) X-SpamScore: 1 X-BigFish: vps1(zzzz1202hzzz32i6bh62h) X-Spam-TCS-SCL: 1:0 X-MS-Exchange-Organization-Antispam-Report: OrigIP: 193.175.82.87; Service: EHS Received: from mail133-tx2 (localhost.localdomain [127.0.0.1]) by mail133-tx2 (MessageSwitch) id 1257876095285849_17298; Tue, 10 Nov 2009 18:01:35 +0000 (UTC) Received: from TX2EHSMHS028.bigfish.com (unknown [10.9.14.251]) by mail133-tx2.bigfish.com (Postfix) with ESMTP id 124301698056 for ; Tue, 10 Nov 2009 18:01:35 +0000 (UTC) Received: from mx1.emlix.com (193.175.82.87) by TX2EHSMHS028.bigfish.com (10.9.99.128) with Microsoft SMTP Server (TLS) id 14.0.482.32; Tue, 10 Nov 2009 18:01:33 +0000 Received: from gate.emlix.com ([193.175.27.217]:35272 helo=mailer.emlix.com) by mx1.emlix.com with esmtp (Exim 4.63) (envelope-from ) id 1N7v23-000419-LU; Tue, 10 Nov 2009 19:01:31 +0100 Received: by mailer.emlix.com id 1N7v23-0003jN-Gk; Tue, 10 Nov 2009 19:01:31 +0100 Received: by avocado.emlix.com (Postfix, from userid 2059) id 3CA14140A8; Tue, 10 Nov 2009 19:01:31 +0100 (CET) From: =?utf-8?q?Daniel=20Gl=C3=B6ckner?= To: Kevin Hilman Date: Tue, 10 Nov 2009 19:01:30 +0100 Message-ID: <1257876090-25156-1-git-send-email-dg@emlix.com> MIME-Version: 1.0 Organization: emlix gmbh, Goettingen, Germany X-Reverse-DNS: mx1.emlix.com Cc: davinci-linux-open-source@linux.davincidsp.com, linux-usb@vger.kernel.org Subject: [PATCH] USB: musb: Fix CPPI IRQs not being signaled X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.4 Precedence: list List-Id: davinci-linux-open-source.linux.davincidsp.com List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: davinci-linux-open-source-bounces@linux.davincidsp.com Errors-To: davinci-linux-open-source-bounces@linux.davincidsp.com diff --git a/drivers/usb/musb/cppi_dma.c b/drivers/usb/musb/cppi_dma.c index c3577bb..ef2332a 100644 --- a/drivers/usb/musb/cppi_dma.c +++ b/drivers/usb/musb/cppi_dma.c @@ -1442,11 +1442,6 @@ static int cppi_channel_abort(struct dma_channel *channel) musb_writew(regs, MUSB_TXCSR, value); musb_writew(regs, MUSB_TXCSR, value); - /* re-enable interrupt */ - if (enabled) - musb_writel(tibase, DAVINCI_TXCPPI_INTENAB_REG, - (1 << cppi_ch->index)); - /* While we scrub the TX state RAM, ensure that we clean * up any interrupt that's currently asserted: * 1. Write to completion Ptr value 0x1(bit 0 set) @@ -1459,6 +1454,11 @@ static int cppi_channel_abort(struct dma_channel *channel) cppi_reset_tx(tx_ram, 1); musb_writel(&tx_ram->tx_complete, 0, 0); + /* re-enable interrupt */ + if (enabled) + musb_writel(tibase, DAVINCI_TXCPPI_INTENAB_REG, + (1 << cppi_ch->index)); + cppi_dump_tx(5, cppi_ch, " (done teardown)"); /* REVISIT tx side _should_ clean up the same way