From patchwork Wed Apr 14 18:44:59 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cyril Chemparathy X-Patchwork-Id: 92469 Received: from bear.ext.ti.com (bear.ext.ti.com [192.94.94.41]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o3EIot7J002381 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Wed, 14 Apr 2010 18:51:31 GMT Received: from dlep36.itg.ti.com ([157.170.170.91]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o3EIn0l8021012 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 14 Apr 2010 13:49:00 -0500 Received: from linux.omap.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o3EIn0ql000343; Wed, 14 Apr 2010 13:49:00 -0500 (CDT) Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id 196CE80677; Wed, 14 Apr 2010 13:48:13 -0500 (CDT) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dlep34.itg.ti.com (dlep34.itg.ti.com [157.170.170.115]) by linux.omap.com (Postfix) with ESMTP id A41FC80628 for ; Wed, 14 Apr 2010 13:45:12 -0500 (CDT) Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id o3EIj9Na006242; Wed, 14 Apr 2010 13:45:09 -0500 (CDT) Received: from gtrgwdeb (gtrgwdeb.telogy.design.ti.com [158.218.102.24]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o3EIj8Z05966; Wed, 14 Apr 2010 13:45:08 -0500 (CDT) Received: by gtrgwdeb (Postfix, from userid 39959) id 79CBF1E068B; Wed, 14 Apr 2010 14:45:06 -0400 (EDT) From: Cyril Chemparathy To: davinci-linux-open-source@linux.davincidsp.com Subject: [PATCH v3 13/16] Davinci: tnetv107x initial support Date: Wed, 14 Apr 2010 14:44:59 -0400 Message-Id: <1271270702-28307-14-git-send-email-cyril@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1271270702-28307-13-git-send-email-cyril@ti.com> References: <1271270702-28307-1-git-send-email-cyril@ti.com> <1271270702-28307-2-git-send-email-cyril@ti.com> <1271270702-28307-3-git-send-email-cyril@ti.com> <1271270702-28307-4-git-send-email-cyril@ti.com> <1271270702-28307-5-git-send-email-cyril@ti.com> <1271270702-28307-6-git-send-email-cyril@ti.com> <1271270702-28307-7-git-send-email-cyril@ti.com> <1271270702-28307-8-git-send-email-cyril@ti.com> <1271270702-28307-9-git-send-email-cyril@ti.com> <1271270702-28307-10-git-send-email-cyril@ti.com> <1271270702-28307-11-git-send-email-cyril@ti.com> <1271270702-28307-12-git-send-email-cyril@ti.com> <1271270702-28307-13-git-send-email-cyril@ti.com> Cc: sshtylyov@mvista.com X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: davinci-linux-open-source-bounces@linux.davincidsp.com Errors-To: davinci-linux-open-source-bounces@linux.davincidsp.com X-Greylist: Sender succeeded STARTTLS authentication, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 14 Apr 2010 18:51:32 +0000 (UTC) diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 0316e20..a67b47b 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -50,6 +50,11 @@ config ARCH_DAVINCI_DM365 select AINTC select ARCH_DAVINCI_DMx +config ARCH_DAVINCI_TNETV107X + select CPU_V6 + select CP_INTC + bool "TNETV107X based system" + comment "DaVinci Board Type" config MACH_DAVINCI_EVM diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index 6aac880..1c7bcfe 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_ARCH_DAVINCI_DM646x) += dm646x.o devices.o obj-$(CONFIG_ARCH_DAVINCI_DM365) += dm365.o devices.o obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da8xx.o obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o devices-da8xx.o +obj-$(CONFIG_ARCH_DAVINCI_TNETV107X) += tnetv107x.o devices-tnetv107x.o obj-$(CONFIG_AINTC) += irq.o obj-$(CONFIG_CP_INTC) += cp_intc.o diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c new file mode 100644 index 0000000..ab54c91 --- /dev/null +++ b/arch/arm/mach-davinci/devices-tnetv107x.c @@ -0,0 +1,128 @@ +/* + * TI TNETV107X platform devices + * + * Author: Cyril Chemparathy + * + * 2009 (c) Texas Instruments, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "clock.h" + +/* Base addresses for on-chip devices */ +#define TNETV107X_TPCC_BASE 0x01c00000 +#define TNETV107X_TPTC0_BASE 0x01c10000 +#define TNETV107X_TPTC1_BASE 0x01c10400 + +/* TNETV107X specific EDMA3 information */ +#define EDMA_TNETV107X_NUM_DMACH 64 +#define EDMA_TNETV107X_NUM_TCC 64 +#define EDMA_TNETV107X_NUM_PARAMENTRY 128 +#define EDMA_TNETV107X_NUM_EVQUE 2 +#define EDMA_TNETV107X_NUM_TC 2 +#define EDMA_TNETV107X_CHMAP_EXIST 0 +#define EDMA_TNETV107X_NUM_REGIONS 4 +#define TNETV107X_DMACH2EVENT_MAP0 0x3C0CE000u +#define TNETV107X_DMACH2EVENT_MAP1 0x000FFFFFu + +static const s8 edma_tc_mapping[][2] = { + /* event queue no TC no */ + { 0, 0 }, + { 1, 1 }, + { -1, -1 } +}; + +static const s8 edma_priority_mapping[][2] = { + /* event queue no Prio */ + { 0, 3 }, + { 1, 7 }, + { -1, -1 } +}; + +static struct edma_soc_info edma_info[] = { + { + .n_channel = EDMA_TNETV107X_NUM_DMACH, + .n_region = EDMA_TNETV107X_NUM_REGIONS, + .n_slot = EDMA_TNETV107X_NUM_PARAMENTRY, + .n_tc = EDMA_TNETV107X_NUM_TC, + .n_cc = 1, + .queue_tc_mapping = edma_tc_mapping, + .queue_priority_mapping = edma_priority_mapping, + }, +}; + +static struct resource edma_resources[] = { + { + .name = "edma_cc0", + .start = TNETV107X_TPCC_BASE, + .end = TNETV107X_TPCC_BASE + SZ_32K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc0", + .start = TNETV107X_TPTC0_BASE, + .end = TNETV107X_TPTC0_BASE + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc1", + .start = TNETV107X_TPTC1_BASE, + .end = TNETV107X_TPTC1_BASE + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma0", + .start = IRQ_TNETV107X_TPCC, + .flags = IORESOURCE_IRQ, + }, + { + .name = "edma0_err", + .start = IRQ_TNETV107X_TPCC_ERR, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device edma_device = { + .name = "edma", + .id = -1, + .num_resources = ARRAY_SIZE(edma_resources), + .resource = edma_resources, + .dev.platform_data = edma_info, +}; + +void __init tnetv107x_edma_init(void) +{ + platform_device_register(&edma_device); +} + +void __init tnetv107x_serial_init(struct plat_serial8250_port* ports) +{ + int i; + char name[16]; + struct clk *uart_clk; + + for (i = 0; ports[i].flags; i++) { + sprintf(name, "uart%d", i); + uart_clk = clk_get(NULL, name); + if (IS_ERR(uart_clk)) + printk(KERN_ERR "%s:%d: failed to get UART%d clock\n", + __func__, __LINE__, i); + else { + clk_enable(uart_clk); + ports[i].uartclk = clk_get_rate(uart_clk); + } + } +} diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c new file mode 100644 index 0000000..a444ef7 --- /dev/null +++ b/arch/arm/mach-davinci/tnetv107x.c @@ -0,0 +1,1175 @@ +/* + * TI TNETV107X chip specific setup + * + * Author: Cyril Chemparathy + * + * 2009 (c) Texas Instruments, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + +/* + * TNETV107X clock control implementation doesn't (at this point) reuse + * much of Davinci's generic implementation. This is because of the + * SSPLL nastiness that is present on this part. + */ + +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clock.h" +#include "mux.h" + +/* Base addresses for on-chip devices */ +#define TNETV107X_INTC_BASE 0x03000000 +#define TNETV107X_TIMER0_BASE 0x08086500 +#define TNETV107X_TIMER1_BASE 0x08086600 +#define TNETV107X_CHIP_CFG_BASE 0x08087000 +#define TNETV107X_CLOCK_CONTROL_BASE 0x0808a000 +#define TNETV107X_PSC_BASE 0x0808b000 + +/* Reference clock frequencies */ +#define OSC_FREQ_ONCHIP (24000 * 1000) +#define OSC_FREQ_OFFCHIP_SYS (25000 * 1000) +#define OSC_FREQ_OFFCHIP_ETH (25000 * 1000) +#define OSC_FREQ_OFFCHIP_TDM (19200 * 1000) + +/* PLL Types */ +enum pll_type { + SYS_PLL, + TDM_PLL, + ETH_PLL, + N_PLLS +}; + +/* Clock Control Registers */ +struct clk_ctrl_regs { + u32 pll_bypass; + u32 _reserved0; + u32 gem_lrst; + u32 _reserved1; + u32 pll_unlock_stat; + u32 sys_unlock; + u32 eth_unlock; + u32 tdm_unlock; +}; + +/* SSPLL Registers */ +struct sspll_regs { + u32 modes; + u32 post_div; + u32 pre_div; + u32 mult_factor; + u32 divider_range; + u32 bw_divider; + u32 spr_amount; + u32 spr_rate_div; + u32 diag; +}; + +static struct clk_ctrl_regs __iomem *clk_ctrl_regs; + +static struct sspll_regs __iomem *sspll_regs[N_PLLS]; +static int sspll_regs_base[N_PLLS] = { 0x40, 0x80, 0xc0 }; + +/* PLL Control Registers (same as in Davinci) */ +static void __iomem *pllctl_regs[N_PLLS]; +static int pllctl_regs_base[N_PLLS] = { 0x600, 0x200, 0x400 }; + +/* PLL bypass bit shifts in clk_ctrl_regs->pll_bypass register */ +static u32 bypass_mask[N_PLLS] = { BIT(0), BIT(2), BIT(1) }; + +/* offchip (external) reference clock frequencies */ +static u32 pll_ext_freq[] = { + OSC_FREQ_OFFCHIP_SYS, + OSC_FREQ_OFFCHIP_TDM, + OSC_FREQ_OFFCHIP_ETH +}; + +/* PSC control registers */ +static void __iomem *psc_regs[1]; + +/* Host map for interrupt controller */ +static u32 intc_host_map[] = { 0x01010000, 0x01010101, -1 }; + +static unsigned long clk_sspll_recalc(struct clk *clk); + +static struct pll_data pll_sys_data = { + .num = SYS_PLL, + .div_ratio_mask = 0x1ff, +}; + +static struct pll_data pll_eth_data = { + .num = ETH_PLL, + .div_ratio_mask = 0xff, +}; + +static struct pll_data pll_tdm_data = { + .num = TDM_PLL, + .div_ratio_mask = 0xff, +}; + +/* Top level of the clock tree - the PLLs */ +static struct clk pll_sys_clk = { + .name = "pll_sys", + .pll_data = &pll_sys_data, + .flags = CLK_PLL, + .recalc = clk_sspll_recalc, +}; + +static struct clk pll_eth_clk = { + .name = "pll_eth", + .pll_data = &pll_eth_data, + .flags = CLK_PLL, + .recalc = clk_sspll_recalc, +}; + +static struct clk pll_tdm_clk = { + .name = "pll_tdm", + .pll_data = &pll_tdm_data, + .flags = CLK_PLL, + .recalc = clk_sspll_recalc, +}; + + +/* System PLL Dividers */ +static struct clk sys_arm1176_clk = { + .name = "sys_arm1176_clk", + .parent = &pll_sys_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV1, +}; + +static struct clk sys_dsp_clk = { + .name = "sys_dsp_clk", + .parent = &pll_sys_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV2, +}; + +static struct clk sys_ddr_clk = { + .name = "sys_ddr_clk", + .parent = &pll_sys_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV3, +}; + +static struct clk sys_full_clk = { + .name = "sys_full_clk", + .parent = &pll_sys_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV4, +}; + +static struct clk sys_lcd_clk = { + .name = "sys_lcd_clk", + .parent = &pll_sys_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV5, +}; + +static struct clk sys_vlynq_ref_clk = { + .name = "sys_vlynq_ref_clk", + .parent = &pll_sys_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV6, +}; + +static struct clk sys_tsc_clk = { + .name = "sys_tsc_clk", + .parent = &pll_sys_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV7, +}; + +static struct clk sys_half_clk = { + .name = "sys_half_clk", + .parent = &pll_sys_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV8, +}; + + +/* Ethernet PLL Dividers */ +static struct clk eth_clk_5 = { + .name = "eth_clk_5", + .parent = &pll_eth_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV1, +}; + +static struct clk eth_clk_50 = { + .name = "eth_clk_50", + .parent = &pll_eth_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV2, +}; + +static struct clk eth_clk_125 = { + .name = "eth_clk_125", + .parent = &pll_eth_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV3, +}; + +static struct clk eth_clk_250 = { + .name = "eth_clk_250", + .parent = &pll_eth_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV4, +}; + +static struct clk eth_clk_25 = { + .name = "eth_clk_25", + .parent = &pll_eth_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV5, +}; + + +/* TDM PLL Dividers */ +static struct clk tdm_0_clk = { + .name = "tdm_0_clk", + .parent = &pll_tdm_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV1, +}; + +static struct clk tdm_extra_clk = { + .name = "tdm_extra_clk", + .parent = &pll_tdm_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV2, +}; + +static struct clk tdm_1_clk = { + .name = "tdm_1_clk", + .parent = &pll_tdm_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV3, +}; + + +/* LPSC Gated Clocks */ +static struct clk clk_arm = { + .name = "arm", + .parent = &sys_arm1176_clk, + .lpsc = TNETV107X_LPSC_ARM, + .flags = ALWAYS_ENABLED, +}; + +static struct clk clk_gem = { + .name = "gem", + .parent = &sys_dsp_clk, + .lpsc = TNETV107X_LPSC_GEM, + .flags = ALWAYS_ENABLED, +}; + +static struct clk clk_ddr2_phy = { + .name = "ddr2_phy", + .parent = &sys_ddr_clk, + .lpsc = TNETV107X_LPSC_DDR2_PHY, + .flags = ALWAYS_ENABLED, +}; + +static struct clk clk_tpcc = { + .name = "tpcc", + .parent = &sys_full_clk, + .lpsc = TNETV107X_LPSC_TPCC, + .flags = ALWAYS_ENABLED, +}; + +static struct clk clk_tptc0 = { + .name = "tptc0", + .parent = &sys_full_clk, + .lpsc = TNETV107X_LPSC_TPTC0, + .flags = ALWAYS_ENABLED, +}; + +static struct clk clk_tptc1 = { + .name = "tptc1", + .parent = &sys_full_clk, + .lpsc = TNETV107X_LPSC_TPTC1, + .flags = ALWAYS_ENABLED, +}; + +static struct clk clk_ram = { + .name = "ram", + .parent = &sys_full_clk, + .lpsc = TNETV107X_LPSC_RAM, + .flags = ALWAYS_ENABLED, +}; + +static struct clk clk_mbx_lite = { + .name = "mbx_lite", + .parent = &sys_arm1176_clk, + .lpsc = TNETV107X_LPSC_MBX_LITE, +}; + +static struct clk clk_lcd = { + .name = "lcd", + .parent = &sys_lcd_clk, + .lpsc = TNETV107X_LPSC_LCD, + .flags = PSC_SWRSTDISABLE, +}; + +static struct clk clk_ethss = { + .name = "ethss", + .parent = ð_clk_125, + .lpsc = TNETV107X_LPSC_ETHSS, +}; + +static struct clk clk_aemif = { + .name = "aemif", + .parent = &sys_full_clk, + .lpsc = TNETV107X_LPSC_AEMIF, + .flags = ALWAYS_ENABLED, +}; + +static struct clk clk_chip_cfg = { + .name = "chip_cfg", + .parent = &sys_half_clk, + .lpsc = TNETV107X_LPSC_CHIP_CFG, + .flags = ALWAYS_ENABLED, +}; + +static struct clk clk_tsc = { + .name = "tsc", + .parent = &sys_tsc_clk, + .lpsc = TNETV107X_LPSC_TSC, +}; + +static struct clk clk_rom = { + .name = "rom", + .parent = &sys_half_clk, + .lpsc = TNETV107X_LPSC_ROM, + .flags = ALWAYS_ENABLED, +}; + +static struct clk clk_uart2 = { + .name = "uart2", + .parent = &sys_half_clk, + .lpsc = TNETV107X_LPSC_UART2, +}; + +static struct clk clk_pktsec = { + .name = "pktsec", + .parent = &sys_half_clk, + .lpsc = TNETV107X_LPSC_PKTSEC, +}; + +static struct clk clk_rng = { + .name = "rng", + .parent = &clk_pktsec, +}; + +static struct clk clk_pka = { + .name = "pka", + .parent = &clk_pktsec, +}; + +static struct clk clk_secctl = { + .name = "secctl", + .parent = &sys_half_clk, + .lpsc = TNETV107X_LPSC_SECCTL, + .flags = ALWAYS_ENABLED, +}; + +static struct clk clk_keymgr = { + .name = "keymgr", + .parent = &sys_half_clk, + .lpsc = TNETV107X_LPSC_KEYMGR, + .flags = ALWAYS_ENABLED, +}; + +static struct clk clk_keypad = { + .name = "keypad", + .parent = &sys_half_clk, + .lpsc = TNETV107X_LPSC_KEYPAD, +}; + +static struct clk clk_gpio = { + .name = "gpio", + .parent = &sys_half_clk, + .lpsc = TNETV107X_LPSC_GPIO, + .flags = ALWAYS_ENABLED, +}; + +static struct clk clk_mdio = { + .name = "mdio", + .parent = &sys_half_clk, + .lpsc = TNETV107X_LPSC_MDIO, +}; + +static struct clk clk_sdio0 = { + .name = "sdio0", + .parent = &sys_half_clk, + .lpsc = TNETV107X_LPSC_SDIO0, +}; + +static struct clk clk_uart0 = { + .name = "uart0", + .parent = &sys_half_clk, + .lpsc = TNETV107X_LPSC_UART0, +}; + +static struct clk clk_uart1 = { + .name = "uart1", + .parent = &sys_half_clk, + .lpsc = TNETV107X_LPSC_UART1, +}; + +static struct clk clk_timer0 = { + .name = "timer0", + .parent = &sys_half_clk, + .lpsc = TNETV107X_LPSC_TIMER0, +}; + +static struct clk clk_timer1 = { + .name = "timer1", + .parent = &sys_half_clk, + .lpsc = TNETV107X_LPSC_TIMER1, +}; + +static struct clk clk_wdt_arm = { + .name = "wdt_arm", + .parent = &sys_half_clk, + .lpsc = TNETV107X_LPSC_WDT_ARM, + .flags = ALWAYS_ENABLED, +}; + +static struct clk clk_wdt_dsp = { + .name = "wdt_dsp", + .parent = &sys_half_clk, + .lpsc = TNETV107X_LPSC_WDT_DSP, +}; + +static struct clk clk_ssp = { + .name = "ssp", + .parent = &sys_half_clk, + .lpsc = TNETV107X_LPSC_SSP, +}; + +static struct clk clk_tdm0 = { + .name = "tdm0", + .parent = &tdm_0_clk, + .lpsc = TNETV107X_LPSC_TDM0, +}; + +static struct clk clk_vlynq = { + .name = "vlynq", + .parent = &sys_vlynq_ref_clk, + .lpsc = TNETV107X_LPSC_VLYNQ, +}; + +static struct clk clk_mcdma = { + .name = "mcdma", + .parent = &sys_half_clk, + .lpsc = TNETV107X_LPSC_MCDMA, +}; + +static struct clk clk_usb0 = { + .name = "usb0", + .parent = &sys_half_clk, + .lpsc = TNETV107X_LPSC_USB0, +}; + +static struct clk clk_tdm1 = { + .name = "tdm1", + .parent = &tdm_1_clk, + .lpsc = TNETV107X_LPSC_TDM1, +}; + +static struct clk clk_debugss = { + .name = "debugss", + .parent = &sys_half_clk, + .lpsc = TNETV107X_LPSC_DEBUGSS, + .flags = ALWAYS_ENABLED, +}; + +static struct clk clk_ethss_rgmii = { + .name = "ethss_rgmii", + .parent = ð_clk_250, + .lpsc = TNETV107X_LPSC_ETHSS_RGMII, +}; + +static struct clk clk_system = { + .name = "system", + .parent = &sys_half_clk, + .lpsc = TNETV107X_LPSC_SYSTEM, + .flags = ALWAYS_ENABLED, +}; + +static struct clk clk_imcop = { + .name = "imcop", + .parent = &sys_dsp_clk, + .lpsc = TNETV107X_LPSC_IMCOP, +}; + +static struct clk clk_spare = { + .name = "spare", + .parent = &sys_half_clk, + .lpsc = TNETV107X_LPSC_SPARE, +}; + +static struct clk clk_sdio1 = { + .name = "sdio1", + .parent = &sys_half_clk, + .lpsc = TNETV107X_LPSC_SDIO1, +}; + +static struct clk clk_usb1 = { + .name = "usb1", + .parent = &sys_half_clk, + .lpsc = TNETV107X_LPSC_USB1, +}; + +static struct clk clk_usbss = { + .name = "usbss", + .parent = &sys_half_clk, + .lpsc = TNETV107X_LPSC_USBSS, +}; + +static struct clk clk_ddr2_vrst = { + .name = "ddr2_vrst", + .parent = &sys_ddr_clk, + .lpsc = TNETV107X_LPSC_DDR2_EMIF1_VRST, + .flags = ALWAYS_ENABLED, +}; + +static struct clk clk_ddr2_vctl_rst = { + .name = "ddr2_vctl_rst", + .parent = &sys_ddr_clk, + .lpsc = TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST, + .flags = ALWAYS_ENABLED, +}; + +static struct clk_lookup tnetv107x_clks[] = { + CLK(NULL, "pll_sys_clk", &pll_sys_clk), + CLK(NULL, "pll_eth_clk", &pll_eth_clk), + CLK(NULL, "pll_tdm_clk", &pll_tdm_clk), + CLK(NULL, "sys_arm1176_clk", &sys_arm1176_clk), + CLK(NULL, "sys_dsp_clk", &sys_dsp_clk), + CLK(NULL, "sys_ddr_clk", &sys_ddr_clk), + CLK(NULL, "sys_full_clk", &sys_full_clk), + CLK(NULL, "sys_lcd_clk", &sys_lcd_clk), + CLK(NULL, "sys_vlynq_ref_clk", &sys_vlynq_ref_clk), + CLK(NULL, "sys_tsc_clk", &sys_tsc_clk), + CLK(NULL, "sys_half_clk", &sys_half_clk), + CLK(NULL, "eth_clk_5", ð_clk_5), + CLK(NULL, "eth_clk_50", ð_clk_50), + CLK(NULL, "eth_clk_125", ð_clk_125), + CLK(NULL, "eth_clk_250", ð_clk_250), + CLK(NULL, "eth_clk_25", ð_clk_25), + CLK(NULL, "tdm_0_clk", &tdm_0_clk), + CLK(NULL, "tdm_extra_clk", &tdm_extra_clk), + CLK(NULL, "tdm_1_clk", &tdm_1_clk), + CLK(NULL, "clk_arm", &clk_arm), + CLK(NULL, "clk_gem", &clk_gem), + CLK(NULL, "clk_ddr2_phy", &clk_ddr2_phy), + CLK(NULL, "clk_tpcc", &clk_tpcc), + CLK(NULL, "clk_tptc0", &clk_tptc0), + CLK(NULL, "clk_tptc1", &clk_tptc1), + CLK(NULL, "clk_ram", &clk_ram), + CLK(NULL, "clk_mbx_lite", &clk_mbx_lite), + CLK("tnetv107x-fb.0", NULL, &clk_lcd), + CLK(NULL, "clk_ethss", &clk_ethss), + CLK(NULL, "aemif", &clk_aemif), + CLK(NULL, "clk_chip_cfg", &clk_chip_cfg), + CLK("tnetv107x-ts.0", NULL, &clk_tsc), + CLK(NULL, "clk_rom", &clk_rom), + CLK(NULL, "uart2", &clk_uart2), + CLK(NULL, "clk_pktsec", &clk_pktsec), + CLK("tnetv107x-rng.0", NULL, &clk_rng), + CLK("tnetv107x-pka.0", NULL, &clk_pka), + CLK(NULL, "clk_secctl", &clk_secctl), + CLK(NULL, "clk_keymgr", &clk_keymgr), + CLK("tnetv107x-keypad.0", NULL, &clk_keypad), + CLK(NULL, "clk_gpio", &clk_gpio), + CLK(NULL, "clk_mdio", &clk_mdio), + CLK("davinci_mmc.0", NULL, &clk_sdio0), + CLK(NULL, "uart0", &clk_uart0), + CLK(NULL, "uart1", &clk_uart1), + CLK(NULL, "timer0", &clk_timer0), + CLK(NULL, "timer1", &clk_timer1), + CLK(NULL, "clk_wdt_arm", &clk_wdt_arm), + CLK(NULL, "clk_wdt_dsp", &clk_wdt_dsp), + CLK("ti-ssp.0", NULL, &clk_ssp), + CLK(NULL, "clk_tdm0", &clk_tdm0), + CLK(NULL, "clk_vlynq", &clk_vlynq), + CLK(NULL, "clk_mcdma", &clk_mcdma), + CLK(NULL, "clk_usb0", &clk_usb0), + CLK(NULL, "clk_tdm1", &clk_tdm1), + CLK(NULL, "clk_debugss", &clk_debugss), + CLK(NULL, "clk_ethss_rgmii", &clk_ethss_rgmii), + CLK(NULL, "clk_system", &clk_system), + CLK(NULL, "clk_imcop", &clk_imcop), + CLK(NULL, "clk_spare", &clk_spare), + CLK("davinci_mmc.1", NULL, &clk_sdio1), + CLK(NULL, "clk_usb1", &clk_usb1), + CLK(NULL, "clk_usbss", &clk_usbss), + CLK(NULL, "clk_ddr2_vrst", &clk_ddr2_vrst), + CLK(NULL, "clk_ddr2_vctl_rst", &clk_ddr2_vctl_rst), + CLK(NULL, NULL, NULL), +}; + +static const struct mux_config tnetv107x_pins[] = { +#ifdef CONFIG_DAVINCI_MUX + MUX_CFG(TNETV107X, ASR_A00, 0, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO32, 0, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A01, 0, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO33, 0, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A02, 0, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO34, 0, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A03, 0, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO35, 0, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A04, 0, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO36, 0, 20, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A05, 0, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO37, 0, 25, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A06, 1, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO38, 1, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A07, 1, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO39, 1, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A08, 1, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO40, 1, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A09, 1, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO41, 1, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A10, 1, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO42, 1, 20, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A11, 1, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, BOOT_STRP_0, 1, 25, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A12, 2, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, BOOT_STRP_1, 2, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A13, 2, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO43, 2, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A14, 2, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO44, 2, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A15, 2, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO45, 2, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A16, 2, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO46, 2, 20, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A17, 2, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO47, 2, 25, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A18, 3, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO48, 3, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO1_DATA3_0, 3, 0, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_A19, 3, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO49, 3, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO1_DATA2_0, 3, 5, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_A20, 3, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO50, 3, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO1_DATA1_0, 3, 10, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_A21, 3, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO51, 3, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO1_DATA0_0, 3, 15, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_A22, 3, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO52, 3, 20, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO1_CMD_0, 3, 20, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_A23, 3, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO53, 3, 25, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO1_CLK_0, 3, 25, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_BA_1, 4, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO54, 4, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SYS_PLL_CLK, 4, 0, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_CS0, 4, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, ASR_CS1, 4, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, ASR_CS2, 4, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDM_PLL_CLK, 4, 15, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_CS3, 4, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, ETH_PHY_CLK, 4, 20, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, ASR_D00, 4, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO55, 4, 25, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D01, 5, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO56, 5, 0, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D02, 5, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO57, 5, 5, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D03, 5, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO58, 5, 10, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D04, 5, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO59_0, 5, 15, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D05, 5, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO60_0, 5, 20, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D06, 5, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO61_0, 5, 25, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D07, 6, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO62_0, 6, 0, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D08, 6, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO63_0, 6, 5, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D09, 6, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO64_0, 6, 10, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D10, 6, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, SDIO1_DATA3_1, 6, 15, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D11, 6, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, SDIO1_DATA2_1, 6, 20, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D12, 6, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, SDIO1_DATA1_1, 6, 25, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D13, 7, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, SDIO1_DATA0_1, 7, 0, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D14, 7, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, SDIO1_CMD_1, 7, 5, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D15, 7, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, SDIO1_CLK_1, 7, 10, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_OE, 7, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, BOOT_STRP_2, 7, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_RNW, 7, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO29_0, 7, 20, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_WAIT, 7, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO30_0, 7, 25, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_WE, 8, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, BOOT_STRP_3, 8, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_WE_DQM0, 8, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO31, 8, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, LCD_PD17_0, 8, 5, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_WE_DQM1, 8, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, ASR_BA0_0, 8, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, VLYNQ_CLK, 9, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO14, 9, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, LCD_PD19_0, 9, 0, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, VLYNQ_RXD0, 9, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO15, 9, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, LCD_PD20_0, 9, 5, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, VLYNQ_RXD1, 9, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO16, 9, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, LCD_PD21_0, 9, 10, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, VLYNQ_TXD0, 9, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO17, 9, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, LCD_PD22_0, 9, 15, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, VLYNQ_TXD1, 9, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO18, 9, 20, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, LCD_PD23_0, 9, 20, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, SDIO0_CLK, 10, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO19, 10, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO0_CMD, 10, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO20, 10, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO0_DATA0, 10, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO21, 10, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO0_DATA1, 10, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO22, 10, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO0_DATA2, 10, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO23, 10, 20, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO0_DATA3, 10, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO24, 10, 25, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, EMU0, 11, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, EMU1, 11, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, RTCK, 12, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TRST_N, 12, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TCK, 12, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDI, 12, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDO, 12, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TMS, 12, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDM1_CLK, 13, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDM1_RX, 13, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDM1_TX, 13, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDM1_FS, 13, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_R0, 14, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_R1, 14, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_R2, 14, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_R3, 14, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_R4, 14, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_R5, 14, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_R6, 15, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO12, 15, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, KEYPAD_R7, 15, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO10, 15, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, KEYPAD_C0, 15, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_C1, 15, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_C2, 15, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_C3, 15, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_C4, 16, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_C5, 16, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_C6, 16, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO13, 16, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, TEST_CLK_IN, 16, 10, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, KEYPAD_C7, 16, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO11, 16, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SSP0_0, 17, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, SCC_DCLK, 17, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, LCD_PD20_1, 17, 0, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, SSP0_1, 17, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, SCC_CS_N, 17, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, LCD_PD21_1, 17, 5, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, SSP0_2, 17, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, SCC_D, 17, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, LCD_PD22_1, 17, 10, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, SSP0_3, 17, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, SCC_RESETN, 17, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, LCD_PD23_1, 17, 15, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, SSP1_0, 18, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO25, 18, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, UART2_CTS, 18, 0, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, SSP1_1, 18, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO26, 18, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, UART2_RD, 18, 5, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, SSP1_2, 18, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO27, 18, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, UART2_RTS, 18, 10, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, SSP1_3, 18, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO28, 18, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, UART2_TD, 18, 15, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, UART0_CTS, 19, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, UART0_RD, 19, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, UART0_RTS, 19, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, UART0_TD, 19, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, UART1_RD, 19, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, UART1_TD, 19, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_AC_NCS, 20, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_HSYNC_RNW, 20, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_VSYNC_A0, 20, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_MCLK, 20, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD16_0, 20, 15, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, LCD_PCLK_E, 20, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD00, 20, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD01, 21, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD02, 21, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD03, 21, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD04, 21, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD05, 21, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD06, 21, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD07, 22, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD08, 22, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO59_1, 22, 5, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, LCD_PD09, 22, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO60_1, 22, 10, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, LCD_PD10, 22, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, ASR_BA0_1, 22, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, GPIO61_1, 22, 15, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, LCD_PD11, 22, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO62_1, 22, 20, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, LCD_PD12, 22, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO63_1, 22, 25, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, LCD_PD13, 23, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO64_1, 23, 0, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, LCD_PD14, 23, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO29_1, 23, 5, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, LCD_PD15, 23, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO30_1, 23, 10, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, EINT0, 24, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO08, 24, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, EINT1, 24, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO09, 24, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, GPIO00, 24, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD20_2, 24, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, TDM_CLK_IN_2, 24, 10, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, GPIO01, 24, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD21_2, 24, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, 24M_CLK_OUT_1, 24, 15, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, GPIO02, 24, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD22_2, 24, 20, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, GPIO03, 24, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD23_2, 24, 25, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, GPIO04, 25, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD16_1, 25, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, USB0_RXERR, 25, 0, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, GPIO05, 25, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD17_1, 25, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, TDM_CLK_IN_1, 25, 5, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, GPIO06, 25, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD18, 25, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, 24M_CLK_OUT_2, 25, 10, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, GPIO07, 25, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD19_1, 25, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, USB1_RXERR, 25, 15, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, ETH_PLL_CLK, 25, 15, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, MDIO, 26, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, MDC, 26, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, AIC_MUTE_STAT_N, 26, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDM0_CLK, 26, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, AIC_HNS_EN_N, 26, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDM0_FS, 26, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, AIC_HDS_EN_STAT_N, 26, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDM0_TX, 26, 20, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, AIC_HNF_EN_STAT_N, 26, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDM0_RX, 26, 25, 0x1f, 0x04, false) +#endif +}; + +/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ +static u8 tnetv107x_irq_prios[TNETV107X_N_CP_INTC_IRQ] = { + [IRQ_TNETV107X_TDM1_TXDMA] = 7, + [IRQ_TNETV107X_EXT_INT_0] = 7, + [IRQ_TNETV107X_EXT_INT_1] = 7, + [IRQ_TNETV107X_GPIO_INT12] = 7, + [IRQ_TNETV107X_GPIO_INT13] = 7, + [IRQ_TNETV107X_TIMER_0_TINT12] = 7, + [IRQ_TNETV107X_TIMER_1_TINT12] = 7, + [IRQ_TNETV107X_UART0] = 7, + [IRQ_TNETV107X_TDM1_RXDMA] = 7, + [IRQ_TNETV107X_MCDMA_INT0] = 7, + [IRQ_TNETV107X_MCDMA_INT1] = 7, + [IRQ_TNETV107X_TPCC] = 7, + [IRQ_TNETV107X_TPCC_INT0] = 7, + [IRQ_TNETV107X_TPCC_INT1] = 7, + [IRQ_TNETV107X_TPCC_INT2] = 7, + [IRQ_TNETV107X_TPCC_INT3] = 7, + [IRQ_TNETV107X_TPTC0] = 7, + [IRQ_TNETV107X_TPTC1] = 7, + [IRQ_TNETV107X_TIMER_0_TINT34] = 7, + [IRQ_TNETV107X_ETHSS] = 7, + [IRQ_TNETV107X_TIMER_1_TINT34] = 7, + [IRQ_TNETV107X_DSP2ARM_INT0] = 7, + [IRQ_TNETV107X_DSP2ARM_INT1] = 7, + [IRQ_TNETV107X_ARM_NPMUIRQ] = 7, + [IRQ_TNETV107X_USB1] = 7, + [IRQ_TNETV107X_VLYNQ] = 7, + [IRQ_TNETV107X_UART0_DMATX] = 7, + [IRQ_TNETV107X_UART0_DMARX] = 7, + [IRQ_TNETV107X_TDM1_TXMCSP] = 7, + [IRQ_TNETV107X_SSP] = 7, + [IRQ_TNETV107X_MCDMA_INT2] = 7, + [IRQ_TNETV107X_MCDMA_INT3] = 7, + [IRQ_TNETV107X_TDM_CODECIF_EOT] = 7, + [IRQ_TNETV107X_IMCOP_SQR_ARM] = 7, + [IRQ_TNETV107X_USB0] = 7, + [IRQ_TNETV107X_USB_CDMA] = 7, + [IRQ_TNETV107X_LCD] = 7, + [IRQ_TNETV107X_KEYPAD] = 7, + [IRQ_TNETV107X_KEYPAD_FREE] = 7, + [IRQ_TNETV107X_RNG] = 7, + [IRQ_TNETV107X_PKA] = 7, + [IRQ_TNETV107X_TDM0_TXDMA] = 7, + [IRQ_TNETV107X_TDM0_RXDMA] = 7, + [IRQ_TNETV107X_TDM0_TXMCSP] = 7, + [IRQ_TNETV107X_TDM0_RXMCSP] = 7, + [IRQ_TNETV107X_TDM1_RXMCSP] = 7, + [IRQ_TNETV107X_SDIO1] = 7, + [IRQ_TNETV107X_SDIO0] = 7, + [IRQ_TNETV107X_TSC] = 7, + [IRQ_TNETV107X_TS] = 7, + [IRQ_TNETV107X_UART1] = 7, + [IRQ_TNETV107X_MBX_LITE] = 7, + [IRQ_TNETV107X_GPIO_INT00] = 7, + [IRQ_TNETV107X_GPIO_INT01] = 7, + [IRQ_TNETV107X_GPIO_INT02] = 7, + [IRQ_TNETV107X_GPIO_INT03] = 7, + [IRQ_TNETV107X_UART2] = 7, + [IRQ_TNETV107X_UART2_DMATX] = 7, + [IRQ_TNETV107X_UART2_DMARX] = 7, + [IRQ_TNETV107X_IMCOP_IMX] = 7, + [IRQ_TNETV107X_IMCOP_VLCD] = 7, + [IRQ_TNETV107X_AES] = 7, + [IRQ_TNETV107X_DES] = 7, + [IRQ_TNETV107X_SHAMD5] = 7, + [IRQ_TNETV107X_TPCC_ERR] = 7, + [IRQ_TNETV107X_TPCC_PROT] = 7, + [IRQ_TNETV107X_TPTC0_ERR] = 7, + [IRQ_TNETV107X_TPTC1_ERR] = 7, + [IRQ_TNETV107X_UART0_ERR] = 7, + [IRQ_TNETV107X_UART1_ERR] = 7, + [IRQ_TNETV107X_AEMIF_ERR] = 7, + [IRQ_TNETV107X_DDR_ERR] = 7, + [IRQ_TNETV107X_WDTARM_INT0] = 7, + [IRQ_TNETV107X_MCDMA_ERR] = 7, + [IRQ_TNETV107X_GPIO_ERR] = 7, + [IRQ_TNETV107X_MPU_ADDR] = 7, + [IRQ_TNETV107X_MPU_PROT] = 7, + [IRQ_TNETV107X_IOPU_ADDR] = 7, + [IRQ_TNETV107X_IOPU_PROT] = 7, + [IRQ_TNETV107X_KEYPAD_ADDR_ERR] = 7, + [IRQ_TNETV107X_WDT0_ADDR_ERR] = 7, + [IRQ_TNETV107X_WDT1_ADDR_ERR] = 7, + [IRQ_TNETV107X_CLKCTL_ADDR_ERR] = 7, + [IRQ_TNETV107X_PLL_UNLOCK] = 7, + [IRQ_TNETV107X_WDTDSP_INT0] = 7, + [IRQ_TNETV107X_SEC_CTRL_VIOLATION] = 7, + [IRQ_TNETV107X_KEY_MNG_VIOLATION] = 7, + [IRQ_TNETV107X_PBIST_CPU] = 7, + [IRQ_TNETV107X_WDTARM] = 7, + [IRQ_TNETV107X_PSC] = 7, + [IRQ_TNETV107X_MMC0] = 7, + [IRQ_TNETV107X_MMC1] = 7, +}; + +/* Contents of JTAG ID register used to identify exact cpu type */ +static struct davinci_id tnetv107x_ids[] = { + { + .variant = 0x0, + .part_no = 0xb8a1, + .manufacturer = 0x017, + .cpu_id = DAVINCI_CPU_ID_TNETV107X, + .name = "tnetv107x rev1.0", + }, +}; + +static struct davinci_timer_instance tnetv107x_timer_instance[2] = { + { + .bottom_irq = IRQ_TNETV107X_TIMER_0_TINT12, + .top_irq = IRQ_TNETV107X_TIMER_0_TINT34, + }, + { + .bottom_irq = IRQ_TNETV107X_TIMER_1_TINT12, + .top_irq = IRQ_TNETV107X_TIMER_1_TINT34, + }, +}; + +static struct davinci_timer_info tnetv107x_timer_info = { + .timers = tnetv107x_timer_instance, + .clockevent_id = T0_BOT, + .clocksource_id = T0_TOP, +}; + +/* + * TNETV107X platforms do not use the static mappings from Davinci + * IO_PHYS/IO_VIRT. This SOC's interesting MMRs are at different addresses, + * and changing IO_PHYS would break away from existing Davinci SOCs. + * + * The primary impact of the current model is that IO_ADDRESS() is not to be + * used to map registers on TNETV107X. With the exception of early boot code + * in tnetv107x_init() (where fixed maps are necessary), all other pieces of + * code absolutely _must_ use ioremap(). + * + * 1. The first section in here is specifically for edma, even through the + * edma driver code properly ioremap()s its register space. This is + * because the edma MMRs on tnetv107x unfortunately fall within the + * davinci IO_PHYS - (IO_PHYS + IO_SIZE) range, and therefore the edma + * driver's ioremap() gets subverted by davinci_ioremap(). Yikes! + * + * 2. The second chunk is for INTC - no major issues here. If the cp_intc + * code were to someday ioremap() internally, we could very well get rid + * of this map. + * + * 3. The third chunk maps in register areas that need to be populated into + * davinci_soc_info. Note that alignment restrictions come into play if + * low-level debug is enabled (see note in ). + */ +static struct map_desc tnetv107x_io_desc[] = { + { /* EDMA */ + .virtual = IO_VIRT, + .pfn = __phys_to_pfn(IO_PHYS), + .length = SZ_128K, + .type = MT_DEVICE + }, + { /* INTC */ + .virtual = IO_VIRT + SZ_128K, + .pfn = __phys_to_pfn(TNETV107X_INTC_BASE), + .length = SZ_16K, + .type = MT_DEVICE + }, + { /* Most of the rest */ + .virtual = TNETV107X_IO_VIRT, + .pfn = __phys_to_pfn(TNETV107X_IO_BASE), + .length = IO_SIZE - SZ_1M, + .type = MT_DEVICE + }, +}; + +static struct davinci_soc_info tnetv107x_soc_info = { + .io_desc = tnetv107x_io_desc, + .io_desc_num = ARRAY_SIZE(tnetv107x_io_desc), + .ids = tnetv107x_ids, + .ids_num = ARRAY_SIZE(tnetv107x_ids), + .cpu_clks = tnetv107x_clks, + .psc_bases = psc_regs, + .psc_bases_num = ARRAY_SIZE(psc_regs), + .pinmux_pins = tnetv107x_pins, + .pinmux_pins_num = ARRAY_SIZE(tnetv107x_pins), + .intc_type = DAVINCI_INTC_TYPE_CP_INTC, + .intc_irq_prios = tnetv107x_irq_prios, + .intc_irq_num = TNETV107X_N_CP_INTC_IRQ, + .timer_info = &tnetv107x_timer_info, +}; + +#define tnetv107x_early_ioremap(p, s) \ + __davinci_ioremap(p, s, \ + tnetv107x_soc_info.io_desc, \ + tnetv107x_soc_info.io_desc_num) + +void __init tnetv107x_init(void) +{ + void __iomem *tmp; + int i; + + /* + * Figure out virtual addresses for necessary peripherals, but do not + * access any of these here. iotable_init() needs to happen for the + * mappings to actually get setup + */ + clk_ctrl_regs = tmp = + tnetv107x_early_ioremap(TNETV107X_CLOCK_CONTROL_BASE, SZ_4K); + + for (i = 0; i < N_PLLS; i++) { + sspll_regs[i] = tmp + sspll_regs_base[i]; + pllctl_regs[i] = tmp + pllctl_regs_base[i]; + } + + pll_sys_data.base = pllctl_regs[SYS_PLL]; + pll_eth_data.base = pllctl_regs[ETH_PLL]; + pll_tdm_data.base = pllctl_regs[TDM_PLL]; + + psc_regs[0] = tnetv107x_early_ioremap(TNETV107X_PSC_BASE, SZ_4K); + + tmp = tnetv107x_early_ioremap(TNETV107X_CHIP_CFG_BASE, SZ_4K); + tnetv107x_soc_info.jtag_id_base = tmp + 0x018; + tnetv107x_soc_info.pinmux_base = tmp + 0x150; + + tnetv107x_soc_info.intc_base = + tnetv107x_early_ioremap(TNETV107X_INTC_BASE, SZ_16K); + + tnetv107x_timer_instance[0].base = + tnetv107x_early_ioremap(TNETV107X_TIMER0_BASE, 0x100); + + tnetv107x_timer_instance[1].base = + tnetv107x_early_ioremap(TNETV107X_TIMER1_BASE, 0x100); + + davinci_common_init(&tnetv107x_soc_info); +} + +void __init tnetv107x_irq_init(void) +{ + struct davinci_soc_info *soc_info = &davinci_soc_info; + + cp_intc_init(soc_info->intc_base, soc_info->intc_irq_num, + soc_info->intc_irq_prios, intc_host_map); +} + +static unsigned long clk_sspll_recalc(struct clk *clk) +{ + int pll; + unsigned long mult = 0, prediv = 1, postdiv = 1; + unsigned long ref = OSC_FREQ_ONCHIP, ret; + u32 tmp; + + if (WARN_ON(!clk->pll_data)) + return clk->rate; + + pll = clk->pll_data->num; + + tmp = __raw_readl(&clk_ctrl_regs->pll_bypass); + if (!(tmp & bypass_mask[pll])) { + mult = __raw_readl(&sspll_regs[pll]->mult_factor); + prediv = __raw_readl(&sspll_regs[pll]->pre_div) + 1; + postdiv = __raw_readl(&sspll_regs[pll]->post_div) + 1; + } + + tmp = __raw_readl(pllctl_regs[pll] + PLLCTL); + if (tmp & PLLCTL_CLKMODE) + ref = pll_ext_freq[pll]; + + clk->pll_data->input_rate = ref; + + tmp = __raw_readl(pllctl_regs[pll] + PLLCTL); + if (!(tmp & PLLCTL_PLLEN)) + return ref; + + ret = ref; + if (mult) + ret += ((unsigned long long)ref * mult) / 256; + + ret /= (prediv * postdiv); + + return ret; +}