[v3,07/16] Davinci: gpio - struct renames

Message ID	1271270702-28307-8-git-send-email-cyril@ti.com (mailing list archive)
State	Changes Requested
Headers	show Received: from comal.ext.ti.com (comal.ext.ti.com [198.47.26.152]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o3EInJRA001921 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for <patchwork-davinci@patchwork.kernel.org>; Wed, 14 Apr 2010 18:49:55 GMT From: Cyril Chemparathy <cyril@ti.com> To: davinci-linux-open-source@linux.davincidsp.com Subject: [PATCH v3 07/16] Davinci: gpio - struct renames Date: Wed, 14 Apr 2010 14:44:53 -0400 Message-Id: <1271270702-28307-8-git-send-email-cyril@ti.com> In-Reply-To: <1271270702-28307-7-git-send-email-cyril@ti.com> References: <1271270702-28307-1-git-send-email-cyril@ti.com> <1271270702-28307-2-git-send-email-cyril@ti.com> <1271270702-28307-3-git-send-email-cyril@ti.com> <1271270702-28307-4-git-send-email-cyril@ti.com> <1271270702-28307-5-git-send-email-cyril@ti.com> <1271270702-28307-6-git-send-email-cyril@ti.com> <1271270702-28307-7-git-send-email-cyril@ti.com> Cc: sshtylyov@mvista.com Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: davinci-linux-open-source-bounces@linux.davincidsp.com Errors-To: davinci-linux-open-source-bounces@linux.davincidsp.com

diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c index 5a045e6..6c470a7 100644 --- a/arch/arm/mach-davinci/gpio.c +++ b/arch/arm/mach-davinci/gpio.c @@ -22,28 +22,22 @@ static DEFINE_SPINLOCK(gpio_lock); -struct davinci_gpio { - struct gpio_chip chip; - struct gpio_controller __iomem *regs; - int irq_base; -}; - #define chip2controller(chip) \ - container_of(chip, struct davinci_gpio, chip) + container_of(chip, struct davinci_gpio_controller, chip) -static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)]; +static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)]; /* create a non-inlined version */ -static struct gpio_controller __iomem __init *gpio2controller(unsigned gpio) +static struct davinci_gpio_regs __iomem __init *gpio2controller(unsigned gpio) { return __gpio_to_controller(gpio); } -static inline struct gpio_controller __iomem *irq2controller(int irq) +static inline struct davinci_gpio_regs __iomem *irq2controller(int irq) { - struct gpio_controller __iomem *g; + struct davinci_gpio_regs __iomem *g; - g = (__force struct gpio_controller __iomem *)get_irq_chip_data(irq); + g = (__force struct davinci_gpio_regs __iomem *)get_irq_chip_data(irq); return g; } @@ -59,8 +53,8 @@ static int __init davinci_gpio_irq_setup(void); static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) { - struct davinci_gpio *d = chip2controller(chip); - struct gpio_controller __iomem *g = d->regs; + struct davinci_gpio_controller *d = chip2controller(chip); + struct davinci_gpio_regs __iomem *g = d->regs; u32 temp; spin_lock(&gpio_lock); @@ -81,8 +75,8 @@ static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) */ static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) { - struct davinci_gpio *d = chip2controller(chip); - struct gpio_controller __iomem *g = d->regs; + struct davinci_gpio_controller *d = chip2controller(chip); + struct davinci_gpio_regs __iomem *g = d->regs; return (1 << offset) & __raw_readl(&g->in_data); } @@ -90,8 +84,8 @@ static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) static int davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) { - struct davinci_gpio *d = chip2controller(chip); - struct gpio_controller __iomem *g = d->regs; + struct davinci_gpio_controller *d = chip2controller(chip); + struct davinci_gpio_regs __iomem *g = d->regs; u32 temp; u32 mask = 1 << offset; @@ -110,8 +104,8 @@ davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) static void davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) { - struct davinci_gpio *d = chip2controller(chip); - struct gpio_controller __iomem *g = d->regs; + struct davinci_gpio_controller *d = chip2controller(chip); + struct davinci_gpio_regs __iomem *g = d->regs; __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data); } @@ -173,7 +167,7 @@ pure_initcall(davinci_gpio_setup); static void gpio_irq_disable(unsigned irq) { - struct gpio_controller __iomem *g = irq2controller(irq); + struct davinci_gpio_regs __iomem *g = irq2controller(irq); u32 mask = (u32) get_irq_data(irq); __raw_writel(mask, &g->clr_falling); @@ -182,7 +176,7 @@ static void gpio_irq_disable(unsigned irq) static void gpio_irq_enable(unsigned irq) { - struct gpio_controller __iomem *g = irq2controller(irq); + struct davinci_gpio_regs __iomem *g = irq2controller(irq); u32 mask = (u32) get_irq_data(irq); unsigned status = irq_desc[irq].status; @@ -198,7 +192,7 @@ static void gpio_irq_enable(unsigned irq) static int gpio_irq_type(unsigned irq, unsigned trigger) { - struct gpio_controller __iomem *g = irq2controller(irq); + struct davinci_gpio_regs __iomem *g = irq2controller(irq); u32 mask = (u32) get_irq_data(irq); if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) @@ -227,7 +221,7 @@ static struct irq_chip gpio_irqchip = { static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) { - struct gpio_controller __iomem *g = irq2controller(irq); + struct davinci_gpio_regs __iomem *g = irq2controller(irq); u32 mask = 0xffff; /* we only care about one bank */ @@ -265,7 +259,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) { - struct davinci_gpio *d = chip2controller(chip); + struct davinci_gpio_controller *d = chip2controller(chip); if (d->irq_base >= 0) return d->irq_base + offset; @@ -288,7 +282,7 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger) { - struct gpio_controller __iomem *g = irq2controller(irq); + struct davinci_gpio_regs __iomem *g = irq2controller(irq); u32 mask = (u32) get_irq_data(irq); if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) @@ -317,7 +311,7 @@ static int __init davinci_gpio_irq_setup(void) u32 binten = 0; unsigned ngpio, bank_irq; struct davinci_soc_info *soc_info = &davinci_soc_info; - struct gpio_controller __iomem *g; + struct davinci_gpio_regs __iomem *g; ngpio = soc_info->gpio_num; diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h index 0099e6e..bdab001 100644 --- a/arch/arm/mach-davinci/include/mach/gpio.h +++ b/arch/arm/mach-davinci/include/mach/gpio.h @@ -45,7 +45,7 @@ /* Convert GPIO signal to GPIO pin number */ #define GPIO_TO_PIN(bank, gpio) (16 * (bank) + (gpio)) -struct gpio_controller { +struct davinci_gpio_regs { u32 dir; u32 out_data; u32 set_data; @@ -58,6 +58,12 @@ struct gpio_controller { u32 intstat; }; +struct davinci_gpio_controller { + struct davinci_gpio_regs __iomem *regs; + struct gpio_chip chip; + int irq_base; +}; + /* The __gpio_to_controller() and __gpio_mask() functions inline to constants * with constant parameters; or in outlined code they execute at runtime. * @@ -67,7 +73,7 @@ struct gpio_controller { * * These are NOT part of the cross-platform GPIO interface */ -static inline struct gpio_controller __iomem * +static inline struct davinci_gpio_regs __iomem * __gpio_to_controller(unsigned gpio) { void __iomem *ptr; @@ -102,7 +108,7 @@ static inline u32 __gpio_mask(unsigned gpio) static inline void gpio_set_value(unsigned gpio, int value) { if (__builtin_constant_p(value) && gpio < DAVINCI_N_GPIO) { - struct gpio_controller __iomem *g; + struct davinci_gpio_regs __iomem *g; u32 mask; g = __gpio_to_controller(gpio); @@ -128,7 +134,7 @@ static inline void gpio_set_value(unsigned gpio, int value) */ static inline int gpio_get_value(unsigned gpio) { - struct gpio_controller __iomem *g; + struct davinci_gpio_regs __iomem *g; if (!__builtin_constant_p(gpio) || gpio >= DAVINCI_N_GPIO) return __gpio_get_value(gpio);

[v3,07/16] Davinci: gpio - struct renames

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