[v3] DaVinci: dm365: Added clockout2 management.

Commit Message

Raffaele Recalcati Aug. 4, 2010, 4:26 p.m. UTC

None

Patch

diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index a717d98..00c4497 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -50,6 +50,9 @@ 
 #define PLLDIV_EN       BIT(15)
 #define PLLDIV_RATIO_MASK 0x1f
 
+#define PERI_CLKCTL	0x48
+#define CLOCKOUT2EN	2
+
 /*
  * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
  * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 42fd4a4..4846b62 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -40,6 +40,38 @@ 
 #include "mux.h"
 
 #define DM365_REF_FREQ		24000000	/* 24 MHz on the DM365 EVM */
+#define DIV1_MASK		0x78		/* DIV1 mask in PERI_CLKCTL */
+
+int dm365_clkout2_set_rate(struct clk *clk, unsigned long rate)
+{
+	int i;
+	unsigned long input;
+	unsigned ratio;
+	u32 regval;
+	static void __iomem *system_module_base;
+
+	/* There must be a parent... */
+	if (WARN_ON(!clk->parent))
+		return 0;
+
+	input = clk->parent->rate;
+
+	if (input > rate)
+		ratio = DIV_ROUND_UP(input, rate) - 1;
+
+	system_module_base = ioremap(DAVINCI_SYSTEM_MODULE_BASE, SZ_4K);
+	regval = __raw_readl(system_module_base + PERI_CLKCTL);
+	regval &= DIV1_MASK;
+	regval |= ratio << 3;
+
+	/* to make changes work stop CLOCKOUT & start it again */
+	regval |= 1 << CLOCKOUT2EN;
+	__raw_writel(regval, system_module_base + PERI_CLKCTL);
+	regval &= ~(1 << CLOCKOUT2EN);
+	__raw_writel(regval, system_module_base + PERI_CLKCTL);
+
+	return 0;
+}
 
 static struct pll_data pll1_data = {
 	.num		= 1,
@@ -124,6 +156,7 @@  static struct clk pll1_sysclk6 = {
 	.parent		= &pll1_clk,
 	.flags		= CLK_PLL,
 	.div_reg	= PLLDIV6,
+	.set_rate	= davinci_set_sysclk_rate,
 };
 
 static struct clk pll1_sysclk7 = {
@@ -145,6 +178,13 @@  static struct clk pll1_sysclk9 = {
 	.parent		= &pll1_clk,
 	.flags		= CLK_PLL,
 	.div_reg	= PLLDIV9,
+	.set_rate	= davinci_set_sysclk_rate,
+};
+
+static struct clk clkout2_clk = {
+	.name		= "clkout2",
+	.parent		= &pll1_sysclk9,
+	.set_rate       = dm365_clkout2_set_rate,
 };
 
 static struct clk pll2_clk = {
@@ -421,6 +461,7 @@  static struct clk_lookup dm365_clks[] = {
 	CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
 	CLK(NULL, "pll1_sysclk8", &pll1_sysclk8),
 	CLK(NULL, "pll1_sysclk9", &pll1_sysclk9),
+	CLK(NULL, "clkout2", &clkout2_clk),
 	CLK(NULL, "pll2", &pll2_clk),
 	CLK(NULL, "pll2_aux", &pll2_aux_clk),
 	CLK(NULL, "clkout1", &clkout1_clk),