From patchwork Wed Aug 4 16:26:14 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raffaele Recalcati X-Patchwork-Id: 117080 Received: from bear.ext.ti.com (bear.ext.ti.com [192.94.94.41]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o74GSRS1013417 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Wed, 4 Aug 2010 16:29:03 GMT Received: from dlep36.itg.ti.com ([157.170.170.91]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o74GQJWr013373 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 4 Aug 2010 11:26:20 -0500 Received: from linux.omap.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o74GQIil004595; Wed, 4 Aug 2010 11:26:19 -0500 (CDT) Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id B58D580627; Wed, 4 Aug 2010 11:26:18 -0500 (CDT) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dflp53.itg.ti.com (dflp53.itg.ti.com [128.247.5.6]) by linux.omap.com (Postfix) with ESMTP id 2A4CB80626 for ; Wed, 4 Aug 2010 11:26:17 -0500 (CDT) Received: from neches.ext.ti.com (localhost [127.0.0.1]) by dflp53.itg.ti.com (8.13.8/8.13.8) with ESMTP id o74GQEm4006465 for ; Wed, 4 Aug 2010 11:26:14 -0500 (CDT) Received: from psmtp.com (na3sys009amx178.postini.com [74.125.149.159]) by neches.ext.ti.com (8.13.7/8.13.7) with SMTP id o74GQCI4030364 for ; Wed, 4 Aug 2010 11:26:12 -0500 Received: from source ([74.125.82.47]) by na3sys009amx178.postini.com ([74.125.148.10]) with SMTP; Wed, 04 Aug 2010 09:26:12 PDT Received: by wwb18 with SMTP id 18so1314862wwb.4 for ; Wed, 04 Aug 2010 09:26:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=Tkm+VDWsvFFypRn7iqbjvNtzc6lvKQdrwi0lAkzV09c=; b=MWKp6Vj2c1r0OWh64kj9rWyThZ4owZubAKfr8oresIS8WR7knenxoOgpGIViUHlxHl 8rZn3y8zpcxqoH/3ksfZwtOhTaypdxjcQTNSKUBXTzOdHnZrVgwa6MA6xnBmdzsS24cd uWLOAQs9pK35yYMiEGe3bx7e+h2U81j/osrJc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=ecFZEcDzf8dXq6oxwNyeRzht4INQYrjCZQ/oGNEkL9H7cvtEO6fX7XcffinBnP+GZv hVQa/x7xormTZodNc0BpXkIbqNpgF27PCIPuzurwXc6Tg+3MidWybpeXIURkqetjwFyS l63lbxaHoPgnyD7zyJVdCXf+6dE0V+XpLAnsw= Received: by 10.227.152.149 with SMTP id g21mr7872666wbw.228.1280939171306; Wed, 04 Aug 2010 09:26:11 -0700 (PDT) Received: from localhost.localdomain (host81-90-static.72-81-b.business.telecomitalia.it [81.72.90.81]) by mx.google.com with ESMTPS id w29sm4427109weq.42.2010.08.04.09.26.08 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 04 Aug 2010 09:26:09 -0700 (PDT) From: Raffaele Recalcati To: davinci-linux-open-source@linux.davincidsp.com Subject: [PATCH v3] DaVinci: dm365: Added clockout2 management. Date: Wed, 4 Aug 2010 18:26:14 +0200 Message-Id: <1280939175-4764-1-git-send-email-lamiaposta71@gmail.com> X-Mailer: git-send-email 1.7.0.4 X-pstn-levels: (S:74.52246/99.90000 CV:99.9000 FC:95.5390 LC:95.5390 R:95.9108 P:95.9108 M:97.0282 C:98.6951 ) X-pstn-settings: 2 (0.5000:0.5000) s cv gt3 gt2 gt1 r p m c X-pstn-addresses: from [db-null] Cc: Raffaele Recalcati , Miguel Aguilar X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: davinci-linux-open-source-bounces@linux.davincidsp.com Errors-To: davinci-linux-open-source-bounces@linux.davincidsp.com X-Greylist: Sender succeeded STARTTLS authentication, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 04 Aug 2010 16:29:03 +0000 (UTC) diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index a717d98..00c4497 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h @@ -50,6 +50,9 @@ #define PLLDIV_EN BIT(15) #define PLLDIV_RATIO_MASK 0x1f +#define PERI_CLKCTL 0x48 +#define CLOCKOUT2EN 2 + /* * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 42fd4a4..4846b62 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -40,6 +40,38 @@ #include "mux.h" #define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */ +#define DIV1_MASK 0x78 /* DIV1 mask in PERI_CLKCTL */ + +int dm365_clkout2_set_rate(struct clk *clk, unsigned long rate) +{ + int i; + unsigned long input; + unsigned ratio; + u32 regval; + static void __iomem *system_module_base; + + /* There must be a parent... */ + if (WARN_ON(!clk->parent)) + return 0; + + input = clk->parent->rate; + + if (input > rate) + ratio = DIV_ROUND_UP(input, rate) - 1; + + system_module_base = ioremap(DAVINCI_SYSTEM_MODULE_BASE, SZ_4K); + regval = __raw_readl(system_module_base + PERI_CLKCTL); + regval &= DIV1_MASK; + regval |= ratio << 3; + + /* to make changes work stop CLOCKOUT & start it again */ + regval |= 1 << CLOCKOUT2EN; + __raw_writel(regval, system_module_base + PERI_CLKCTL); + regval &= ~(1 << CLOCKOUT2EN); + __raw_writel(regval, system_module_base + PERI_CLKCTL); + + return 0; +} static struct pll_data pll1_data = { .num = 1, @@ -124,6 +156,7 @@ static struct clk pll1_sysclk6 = { .parent = &pll1_clk, .flags = CLK_PLL, .div_reg = PLLDIV6, + .set_rate = davinci_set_sysclk_rate, }; static struct clk pll1_sysclk7 = { @@ -145,6 +178,13 @@ static struct clk pll1_sysclk9 = { .parent = &pll1_clk, .flags = CLK_PLL, .div_reg = PLLDIV9, + .set_rate = davinci_set_sysclk_rate, +}; + +static struct clk clkout2_clk = { + .name = "clkout2", + .parent = &pll1_sysclk9, + .set_rate = dm365_clkout2_set_rate, }; static struct clk pll2_clk = { @@ -421,6 +461,7 @@ static struct clk_lookup dm365_clks[] = { CLK(NULL, "pll1_sysclk7", &pll1_sysclk7), CLK(NULL, "pll1_sysclk8", &pll1_sysclk8), CLK(NULL, "pll1_sysclk9", &pll1_sysclk9), + CLK(NULL, "clkout2", &clkout2_clk), CLK(NULL, "pll2", &pll2_clk), CLK(NULL, "pll2_aux", &pll2_aux_clk), CLK(NULL, "clkout1", &clkout1_clk),