@@ -19,6 +19,55 @@
#include <mach/cp_intc.h>
#include <mach/da8xx.h>
+#include <mach/mux.h>
+
+#define DA850_EVM_PHY_ID "0:07"
+
+static const short hawk_mii_pins[] = {
+ DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
+ DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
+ DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
+ DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
+ DA850_MDIO_D,
+ -1
+};
+
+static int __init omapl138_hawk_config_emac(void)
+{
+ void __iomem *cfg_chip3_base;
+ int ret;
+ u32 val;
+ struct davinci_soc_info *soc_info = &davinci_soc_info;
+
+ if (!machine_is_omapl138_hawkboard())
+ return 0;
+
+ cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
+
+ val = __raw_readl(cfg_chip3_base);
+
+ val &= ~BIT(8);
+ ret = davinci_cfg_reg_list(hawk_mii_pins);
+ pr_info("EMAC: MII PHY configured, RMII PHY will not be"
+ " functional\n");
+
+ if (ret)
+ pr_warning("hawk_init: cpgmac/rmii mux setup failed: %d\n",
+ ret);
+
+ /* configure the CFGCHIP3 register for MII */
+ __raw_writel(val, cfg_chip3_base);
+
+ /* Enable/Disable MII MDIO clock */
+ soc_info->emac_pdata->phy_id = DA850_EVM_PHY_ID;
+
+ ret = da8xx_register_emac();
+ if (ret)
+ pr_warning("hawk_init: emac registration failed: %d\n",
+ ret);
+ return 0;
+}
+device_initcall(omapl138_hawk_config_emac);
static struct davinci_uart_config omapl138_hawk_uart_config __initdata = {
.enabled_uarts = 0x7,