@@ -736,6 +736,26 @@ static struct edma_rsv_info *da850_edma_rsv[2] = {
&da850_edma_cc1_rsv,
};
+static int __init da850_evm_setup_pru_suart(void)
+{
+ int ret;
+
+ if (!machine_is_davinci_da850_evm())
+ return 0;
+
+ ret = davinci_cfg_reg_list(da850_pru_suart_pins);
+ if (ret)
+ pr_warning("da850_evm_init: da850_pru_suart_pins"
+ "mux setup failed: %d\n", ret);
+ ret = da8xx_register_pru_suart();
+ if (ret)
+ pr_warning("da850_evm_init: pru suart registration"
+ "failed: %d\n", ret);
+ return ret;
+}
+
+device_initcall(da850_evm_setup_pru_suart);
+
static __init void da850_evm_init(void)
{
int ret;
@@ -238,6 +238,13 @@ static struct clk tptc2_clk = {
.flags = ALWAYS_ENABLED,
};
+static struct clk pru_clk = {
+ .name = "pru_ck",
+ .parent = &pll0_sysclk2,
+ .lpsc = DA8XX_LPSC0_DMAX,
+ .flags = ALWAYS_ENABLED,
+};
+
static struct clk uart0_clk = {
.name = "uart0",
.parent = &pll0_sysclk2,
@@ -318,6 +325,14 @@ static struct clk mcasp_clk = {
.flags = DA850_CLK_ASYNC3,
};
+static struct clk mcasp_pru_clk = {
+ .name = "mcasp_pru",
+ .parent = &pll0_sysclk2,
+ .lpsc = DA8XX_LPSC1_McASP0,
+ .gpsc = 1,
+ .flags = DA850_CLK_ASYNC3,
+};
+
static struct clk lcdc_clk = {
.name = "lcdc",
.parent = &pll0_sysclk2,
@@ -373,6 +388,7 @@ static struct clk_lookup da850_clks[] = {
CLK(NULL, "tpcc1", &tpcc1_clk),
CLK(NULL, "tptc2", &tptc2_clk),
CLK(NULL, "uart0", &uart0_clk),
+ CLK(NULL, "pru_ck", &pru_clk),
CLK(NULL, "uart1", &uart1_clk),
CLK(NULL, "uart2", &uart2_clk),
CLK(NULL, "aintc", &aintc_clk),
@@ -382,6 +398,7 @@ static struct clk_lookup da850_clks[] = {
CLK(NULL, "arm", &arm_clk),
CLK(NULL, "rmii", &rmii_clk),
CLK("davinci_emac.1", NULL, &emac_clk),
+ CLK(NULL, "mcasp_pru", &mcasp_pru_clk),
CLK("davinci-mcasp.0", NULL, &mcasp_clk),
CLK("da8xx_lcdc.0", NULL, &lcdc_clk),
CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
@@ -392,9 +409,13 @@ static struct clk_lookup da850_clks[] = {
/*
* Device specific mux setup
- *
- * soc description mux mode mode mux dbg
- * reg offset mask mode
+ * soc -> DA850
+ * desc -> Pin name, which evaluates to soc##_##desc.
+ * muxreg -> Pin Multiplexing Control n (PINMUXn) Register number.
+ * mode_offset -> Bit offset in the register PINMUXn.
+ * mode_mask -> Number of bits for Pin Multiplexing Control n.
+ * mux_mode -> Multiplexing mode to set.
+ * dbg -> debug on/off
*/
static const struct mux_config da850_pins[] = {
#ifdef CONFIG_DAVINCI_MUX
@@ -557,6 +578,14 @@ const short da850_uart0_pins[] __initdata = {
-1
};
+const short da850_pru_suart_pins[] __initdata = {
+ DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
+ DA850_AHCLKR, DA850_ACLKR, DA850_AFSR,
+ DA850_AXR_13, DA850_AXR_9, DA850_AXR_7,
+ DA850_AXR_14, DA850_AXR_10, DA850_AXR_8,
+ -1
+};
+
const short da850_uart1_pins[] __initdata = {
DA850_UART1_RXD, DA850_UART1_TXD,
-1
@@ -14,7 +14,7 @@
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/serial_8250.h>
-
+#include <linux/ti_omapl_pru_suart.h>
#include <mach/cputype.h>
#include <mach/common.h>
#include <mach/time.h>
@@ -85,7 +85,107 @@ struct platform_device da8xx_serial_device = {
},
};
-static const s8 da8xx_queue_tc_mapping[][2] = {
+
+#define OMAPL138_PRU_MEM_BASE 0x01C30000
+
+#define OMAPL138_INT_PRU_SUART_1 IRQ_DA8XX_EVTOUT0
+#define OMAPL138_INT_PRU_SUART_2 IRQ_DA8XX_EVTOUT1
+#define OMAPL138_INT_PRU_SUART_3 IRQ_DA8XX_EVTOUT2
+#define OMAPL138_INT_PRU_SUART_4 IRQ_DA8XX_EVTOUT3
+#define OMAPL138_INT_PRU_SUART_5 IRQ_DA8XX_EVTOUT4
+#define OMAPL138_INT_PRU_SUART_6 IRQ_DA8XX_EVTOUT5
+#define OMAPL138_INT_PRU_SUART_7 IRQ_DA8XX_EVTOUT6
+#define OMAPL138_INT_PRU_SUART_8 IRQ_DA8XX_EVTOUT7
+
+static struct resource omapl138_pru_suart_resources[] = {
+ {
+ .name = "omapl_pru_suart",
+ .start = OMAPL138_PRU_MEM_BASE,
+ .end = OMAPL138_PRU_MEM_BASE + 0xFFFF,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = DAVINCI_DA8XX_MCASP0_REG_BASE,
+ .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = DA8XX_PSC0_BASE,
+ .end = DA8XX_PSC0_BASE + (SZ_1K * 3) - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = DA8XX_PSC1_BASE,
+ .end = DA8XX_PSC1_BASE + (SZ_1K * 3) - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = DA8XX_SHARED_RAM_BASE,
+ .end = DA8XX_SHARED_RAM_BASE + (SZ_1K * 8) - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = OMAPL138_INT_PRU_SUART_1,
+ .end = OMAPL138_INT_PRU_SUART_1,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = OMAPL138_INT_PRU_SUART_2,
+ .end = OMAPL138_INT_PRU_SUART_2,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = OMAPL138_INT_PRU_SUART_3,
+ .end = OMAPL138_INT_PRU_SUART_3,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = OMAPL138_INT_PRU_SUART_4,
+ .end = OMAPL138_INT_PRU_SUART_4,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = OMAPL138_INT_PRU_SUART_5,
+ .end = OMAPL138_INT_PRU_SUART_5,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = OMAPL138_INT_PRU_SUART_6,
+ .end = OMAPL138_INT_PRU_SUART_6,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = OMAPL138_INT_PRU_SUART_7,
+ .end = OMAPL138_INT_PRU_SUART_7,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = OMAPL138_INT_PRU_SUART_8,
+ .end = OMAPL138_INT_PRU_SUART_8,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device omapl_pru_suart_device = {
+ .name = "davinci_pru_suart",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(omapl138_pru_suart_resources),
+ .resource = omapl138_pru_suart_resources,
+};
+
+#define OMAPL138_PRU_SUART_VERSION 1
+
+static struct ti_pru_suart_platform_data ti_pru_suart_pdata = {
+ .version = OMAPL138_PRU_SUART_VERSION,
+};
+
+int __init da8xx_register_pru_suart(void)
+{
+ omapl_pru_suart_device.dev.platform_data = &ti_pru_suart_pdata;
+ return platform_device_register(&omapl_pru_suart_device);
+}
+
+static const s8 da8xx_queue_tc_mapping[][2] = {
/* {event queue no, TC no} */
{0, 0},
{1, 1},
@@ -74,6 +74,7 @@ int da8xx_register_watchdog(void);
int da8xx_register_usb20(unsigned mA, unsigned potpgt);
int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata);
int da8xx_register_emac(void);
+int da8xx_register_pru_suart(void);
int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata);
int da8xx_register_mmcsd0(struct davinci_mmc_config *config);
int da850_register_mmcsd1(struct davinci_mmc_config *config);
@@ -122,6 +123,7 @@ extern const short da850_uart2_pins[];
extern const short da850_i2c0_pins[];
extern const short da850_i2c1_pins[];
extern const short da850_cpgmac_pins[];
+extern const short da850_pru_suart_pins[];
extern const short da850_mcasp_pins[];
extern const short da850_lcdcntl_pins[];
extern const short da850_mmcsd0_pins[];
@@ -22,6 +22,7 @@
**************************************************************************/
#define DAVINCI_DDR_BASE 0x80000000
#define DA8XX_DDR_BASE 0xc0000000
+#define DA8XX_SHARED_RAM_BASE 0x80000000
#if defined(CONFIG_ARCH_DAVINCI_DA8XX) && defined(CONFIG_ARCH_DAVINCI_DMx)
#error Cannot enable DaVinci and DA8XX platforms concurrently
@@ -199,6 +199,9 @@
/* TI OMAP-UART */
#define PORT_OMAP 96
+/* omapl pru uart emulation */
+#define OMAPL_PRU_SUART 97
+
#ifdef __KERNEL__
#include <linux/compiler.h>
new file mode 100644
@@ -0,0 +1,38 @@
+/*
+ * linux/include/linux/ti_omapl_pru_suart.h
+ */
+#ifndef _LINUX_SUART_OMAPL_PRU_H
+#define _LINUX_SUART_OMAPL_PRU_H
+
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+
+/*
+ * TI OMAPL PRU SUART Emulation device driver
+ *
+ * This driver supports TI's PRU SUART Emulation and the
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * struct ti_pru_suart_platform_data - SUART Platform Data
+ *
+ * @version: version for future use
+ *
+ * Platform data structure to get all platform specific settings.
+ */
+
+struct ti_pru_suart_platform_data {
+ u32 version;
+};
+#endif