diff --git a/arch/arm/mach-davinci/include/mach/pru/omapl_mcasp.h b/arch/arm/mach-davinci/include/mach/pru/omapl_mcasp.h
new file mode 100644
index 0000000..c4c1843
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/pru/omapl_mcasp.h
@@ -0,0 +1,498 @@
+/*
+ * Copyright (C) 2010 Texas Instruments Incorporated
+ * Author: Jitendra Kumar <jitendra@mistralsolutions.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as  published by the
+ * Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ */
+
+#ifndef _OMAPLR_MCASP_H_
+#define _OMAPLR_MCASP_H_
+
+#include <linux/types.h>
+#include <mach/pru/omapl_pru.h>
+
+typedef struct {
+	volatile u32 REVID;
+	volatile u32 RSVD0[3];
+	volatile u32 PFUNC;
+	volatile u32 PDIR;
+	volatile u32 PDOUT;
+	volatile u32 PDIN;
+	volatile u32 PDCLR;
+	volatile u32 RSVD1[8];
+	volatile u32 GBLCTL;
+	volatile u32 AMUTE;
+	volatile u32 DLBCTL;
+	volatile u32 DITCTL;
+	volatile u32 RSVD2[3];
+	volatile u32 RGBLCTL;
+	volatile u32 RMASK;
+	volatile u32 RFMT;
+	volatile u32 AFSRCTL;
+	volatile u32 ACLKRCTL;
+	volatile u32 AHCLKRCTL;
+	volatile u32 RTDM;
+	volatile u32 RINTCTL;
+	volatile u32 RSTAT;
+	volatile u32 RSLOT;
+	volatile u32 RCLKCHK;
+	volatile u32 REVTCTL;
+	volatile u32 RSVD3[4];
+	volatile u32 XGBLCTL;
+	volatile u32 XMASK;
+	volatile u32 XFMT;
+	volatile u32 AFSXCTL;
+	volatile u32 ACLKXCTL;
+	volatile u32 AHCLKXCTL;
+	volatile u32 XTDM;
+	volatile u32 XINTCTL;
+	volatile u32 XSTAT;
+	volatile u32 XSLOT;
+	volatile u32 XCLKCHK;
+	volatile u32 XEVTCTL;
+	volatile u32 RSVD4[12];
+	volatile u32 DITCSRA0;
+	volatile u32 DITCSRA1;
+	volatile u32 DITCSRA2;
+	volatile u32 DITCSRA3;
+	volatile u32 DITCSRA4;
+	volatile u32 DITCSRA5;
+	volatile u32 DITCSRB0;
+	volatile u32 DITCSRB1;
+	volatile u32 DITCSRB2;
+	volatile u32 DITCSRB3;
+	volatile u32 DITCSRB4;
+	volatile u32 DITCSRB5;
+	volatile u32 DITUDRA0;
+	volatile u32 DITUDRA1;
+	volatile u32 DITUDRA2;
+	volatile u32 DITUDRA3;
+	volatile u32 DITUDRA4;
+	volatile u32 DITUDRA5;
+	volatile u32 DITUDRB0;
+	volatile u32 DITUDRB1;
+	volatile u32 DITUDRB2;
+	volatile u32 DITUDRB3;
+	volatile u32 DITUDRB4;
+	volatile u32 DITUDRB5;
+	volatile u32 RSVD5[8];
+	volatile u32 SRCTL0;
+	volatile u32 SRCTL1;
+	volatile u32 SRCTL2;
+	volatile u32 SRCTL3;
+	volatile u32 SRCTL4;
+	volatile u32 SRCTL5;
+	volatile u32 SRCTL6;
+	volatile u32 SRCTL7;
+	volatile u32 SRCTL8;
+	volatile u32 SRCTL9;
+	volatile u32 SRCTL10;
+	volatile u32 SRCTL11;
+	volatile u32 SRCTL12;
+	volatile u32 SRCTL13;
+	volatile u32 SRCTL14;
+	volatile u32 SRCTL15;
+	volatile u32 RSVD6[16];
+	volatile u32 XBUF0;
+	volatile u32 XBUF1;
+	volatile u32 XBUF2;
+	volatile u32 XBUF3;
+	volatile u32 XBUF4;
+	volatile u32 XBUF5;
+	volatile u32 XBUF6;
+	volatile u32 XBUF7;
+	volatile u32 XBUF8;
+	volatile u32 XBUF9;
+	volatile u32 XBUF10;
+	volatile u32 XBUF11;
+	volatile u32 XBUF12;
+	volatile u32 XBUF13;
+	volatile u32 XBUF14;
+	volatile u32 XBUF15;
+	volatile u32 RSVD7[16];
+	volatile u32 RBUF0;
+	volatile u32 RBUF1;
+	volatile u32 RBUF2;
+	volatile u32 RBUF3;
+	volatile u32 RBUF4;
+	volatile u32 RBUF5;
+	volatile u32 RBUF6;
+	volatile u32 RBUF7;
+	volatile u32 RBUF8;
+	volatile u32 RBUF9;
+	volatile u32 RBUF10;
+	volatile u32 RBUF11;
+	volatile u32 RBUF12;
+	volatile u32 RBUF13;
+	volatile u32 RBUF14;
+	volatile u32 RBUF15;
+} OMAPL_McaspRegs, *OMAPL_McaspRegsOvly;
+
+
+#define OMAPL_MCASP_PFUNC_AFSR_MASK				(0x80000000u)
+#define OMAPL_MCASP_PFUNC_AFSR_SHIFT			(0x0000001Fu)
+#define OMAPL_MCASP_PFUNC_AFSR_RESETVAL			(0x00000000u)
+/* AFSR Tokens */
+#define OMAPL_MCASP_PFUNC_AFSR_MCASP			(0x00000000u)
+#define OMAPL_MCASP_PFUNC_AFSR_GPIO				(0x00000001u)
+
+#define OMAPL_MCASP_PFUNC_AHCLKR_MASK			(0x40000000u)
+#define OMAPL_MCASP_PFUNC_AHCLKR_SHIFT			(0x0000001Eu)
+#define OMAPL_MCASP_PFUNC_AHCLKR_RESETVAL		(0x00000000u)
+/* AHCLKR Tokens */
+#define OMAPL_MCASP_PFUNC_AHCLKR_MCASP			(0x00000000u)
+#define OMAPL_MCASP_PFUNC_AHCLKR_GPIO			(0x00000001u)
+
+#define OMAPL_MCASP_PFUNC_ACLKR_MASK			(0x20000000u)
+#define OMAPL_MCASP_PFUNC_ACLKR_SHIFT			(0x0000001Du)
+#define OMAPL_MCASP_PFUNC_ACLKR_RESETVAL		(0x00000000u)
+/* ACLKR Tokens */
+#define OMAPL_MCASP_PFUNC_ACLKR_MCASP			(0x00000000u)
+#define OMAPL_MCASP_PFUNC_ACLKR_GPIO			(0x00000001u)
+
+#define OMAPL_MCASP_PFUNC_AFSX_MASK				(0x10000000u)
+#define OMAPL_MCASP_PFUNC_AFSX_SHIFT			(0x0000001Cu)
+#define OMAPL_MCASP_PFUNC_AFSX_RESETVAL			(0x00000000u)
+/* AFSX Tokens */
+#define OMAPL_MCASP_PFUNC_AFSX_MCASP			(0x00000000u)
+#define OMAPL_MCASP_PFUNC_AFSX_GPIO				(0x00000001u)
+
+#define OMAPL_MCASP_PFUNC_AHCLKX_MASK			(0x08000000u)
+#define OMAPL_MCASP_PFUNC_AHCLKX_SHIFT			(0x0000001Bu)
+#define OMAPL_MCASP_PFUNC_AHCLKX_RESETVAL		(0x00000000u)
+/* AHCLKX Tokens */
+#define OMAPL_MCASP_PFUNC_AHCLKX_MCASP			(0x00000000u)
+#define OMAPL_MCASP_PFUNC_AHCLKX_GPIO			(0x00000001u)
+
+#define OMAPL_MCASP_PFUNC_ACLKX_MASK			(0x04000000u)
+#define OMAPL_MCASP_PFUNC_ACLKX_SHIFT			(0x0000001Au)
+#define OMAPL_MCASP_PFUNC_ACLKX_RESETVAL		(0x00000000u)
+/* ACLKX Tokens */
+#define OMAPL_MCASP_PFUNC_ACLKX_MCASP			(0x00000000u)
+#define OMAPL_MCASP_PFUNC_ACLKX_GPIO			(0x00000001u)
+
+#define OMAPL_MCASP_PFUNC_AMUTE_MASK			(0x02000000u)
+#define OMAPL_MCASP_PFUNC_AMUTE_SHIFT			(0x00000019u)
+#define OMAPL_MCASP_PFUNC_AMUTE_RESETVAL		(0x00000000u)
+/* AMUTE Tokens */
+#define OMAPL_MCASP_PFUNC_AMUTE_MCASP			(0x00000000u)
+#define OMAPL_MCASP_PFUNC_AMUTE_GPIO			(0x00000001u)
+
+#define OMAPL_MCASP_PFUNC_AXR15_MASK			(0x00008000u)
+#define OMAPL_MCASP_PFUNC_AXR15_SHIFT			(0x0000000Fu)
+#define OMAPL_MCASP_PFUNC_AXR15_RESETVAL		(0x00000000u)
+#define OMAPL_MCASP_PFUNC_AXR15_MCASP			(0x00000000u)
+#define OMAPL_MCASP_PFUNC_AXR15_GPIO			(0x00000001u)
+
+#define OMAPL_MCASP_PFUNC_AXR14_MASK			(0x00004000u)
+#define OMAPL_MCASP_PFUNC_AXR14_SHIFT			(0x0000000Eu)
+#define OMAPL_MCASP_PFUNC_AXR14_RESETVAL		(0x00000000u)
+#define OMAPL_MCASP_PFUNC_AXR14_MCASP			(0x00000000u)
+#define OMAPL_MCASP_PFUNC_AXR14_GPIO			(0x00000001u)
+
+#define OMAPL_MCASP_PFUNC_AXR13_MASK			(0x00002000u)
+#define OMAPL_MCASP_PFUNC_AXR13_SHIFT			(0x0000000Du)
+#define OMAPL_MCASP_PFUNC_AXR13_RESETVAL		(0x00000000u)
+#define OMAPL_MCASP_PFUNC_AXR13_MCASP			(0x00000000u)
+#define OMAPL_MCASP_PFUNC_AXR13_GPIO			(0x00000001u)
+
+#define OMAPL_MCASP_PFUNC_AXR12_MASK			(0x00001000u)
+#define OMAPL_MCASP_PFUNC_AXR12_SHIFT			(0x0000000Cu)
+#define OMAPL_MCASP_PFUNC_AXR12_RESETVAL		(0x00000000u)
+#define OMAPL_MCASP_PFUNC_AXR12_MCASP			(0x00000000u)
+#define OMAPL_MCASP_PFUNC_AXR12_GPIO			(0x00000001u)
+
+#define OMAPL_MCASP_PFUNC_AXR11_MASK			(0x00000800u)
+#define OMAPL_MCASP_PFUNC_AXR11_SHIFT			(0x0000000Bu)
+#define OMAPL_MCASP_PFUNC_AXR11_RESETVAL		(0x00000000u)
+#define OMAPL_MCASP_PFUNC_AXR11_MCASP			(0x00000000u)
+#define OMAPL_MCASP_PFUNC_AXR11_GPIO			(0x00000001u)
+
+#define OMAPL_MCASP_PFUNC_AXR10_MASK			(0x00000400u)
+#define OMAPL_MCASP_PFUNC_AXR10_SHIFT			(0x0000000Au)
+#define OMAPL_MCASP_PFUNC_AXR10_RESETVAL		(0x00000000u)
+#define OMAPL_MCASP_PFUNC_AXR10_MCASP			(0x00000000u)
+#define OMAPL_MCASP_PFUNC_AXR10_GPIO			(0x00000001u)
+#define OMAPL_MCASP_PFUNC_AXR9_MASK				(0x00000200u)
+#define OMAPL_MCASP_PFUNC_AXR9_SHIFT			(0x00000009u)
+#define OMAPL_MCASP_PFUNC_AXR9_RESETVAL			(0x00000000u)
+/* AXR9 Token */
+#define OMAPL_MCASP_PFUNC_AXR9_MCASP			(0x00000000u)
+#define OMAPL_MCASP_PFUNC_AXR9_GPIO				(0x00000001u)
+
+#define OMAPL_MCASP_PFUNC_AXR8_MASK				(0x00000100u)
+#define OMAPL_MCASP_PFUNC_AXR8_SHIFT			(0x00000008u)
+#define OMAPL_MCASP_PFUNC_AXR8_RESETVAL			(0x00000000u)
+/* AXR8 Tokens */
+#define OMAPL_MCASP_PFUNC_AXR8_MCASP			(0x00000000u)
+#define OMAPL_MCASP_PFUNC_AXR8_GPIO				(0x00000001u)
+
+#define OMAPL_MCASP_PFUNC_AXR7_MASK				(0x00000080u)
+#define OMAPL_MCASP_PFUNC_AXR7_SHIFT			(0x00000007u)
+#define OMAPL_MCASP_PFUNC_AXR7_RESETVAL			(0x00000000u)
+/* AXR7 Tokens */
+#define OMAPL_MCASP_PFUNC_AXR7_MCASP			(0x00000000u)
+#define OMAPL_MCASP_PFUNC_AXR7_GPIO				(0x00000001u)
+
+#define OMAPL_MCASP_PFUNC_AXR6_MASK				(0x00000040u)
+#define OMAPL_MCASP_PFUNC_AXR6_SHIFT			(0x00000006u)
+#define OMAPL_MCASP_PFUNC_AXR6_RESETVAL			(0x00000000u)
+/* AXR6 Tokens */
+#define OMAPL_MCASP_PFUNC_AXR6_MCASP			(0x00000000u)
+#define OMAPL_MCASP_PFUNC_AXR6_GPIO				(0x00000001u)
+
+#define OMAPL_MCASP_PFUNC_AXR5_MASK				(0x00000020u)
+#define OMAPL_MCASP_PFUNC_AXR5_SHIFT			(0x00000005u)
+#define OMAPL_MCASP_PFUNC_AXR5_RESETVAL			(0x00000000u)
+/* AXR5 Tokens */
+#define OMAPL_MCASP_PFUNC_AXR5_MCASP			(0x00000000u)
+#define OMAPL_MCASP_PFUNC_AXR5_GPIO				(0x00000001u)
+
+#define OMAPL_MCASP_PFUNC_AXR4_MASK				(0x00000010u)
+#define OMAPL_MCASP_PFUNC_AXR4_SHIFT			(0x00000004u)
+#define OMAPL_MCASP_PFUNC_AXR4_RESETVAL			(0x00000000u)
+/* AXR4 Tokens */
+#define OMAPL_MCASP_PFUNC_AXR4_MCASP			(0x00000000u)
+#define OMAPL_MCASP_PFUNC_AXR4_GPIO				(0x00000001u)
+
+#define OMAPL_MCASP_PFUNC_AXR3_MASK				(0x00000008u)
+#define OMAPL_MCASP_PFUNC_AXR3_SHIFT			(0x00000003u)
+#define OMAPL_MCASP_PFUNC_AXR3_RESETVAL			(0x00000000u)
+/* AXR3 Tokens */
+#define OMAPL_MCASP_PFUNC_AXR3_MCASP			(0x00000000u)
+#define OMAPL_MCASP_PFUNC_AXR3_GPIO				(0x00000001u)
+
+#define OMAPL_MCASP_PFUNC_AXR2_MASK				(0x00000004u)
+#define OMAPL_MCASP_PFUNC_AXR2_SHIFT			(0x00000002u)
+#define OMAPL_MCASP_PFUNC_AXR2_RESETVAL			(0x00000000u)
+/* AXR2 Tokens */
+#define OMAPL_MCASP_PFUNC_AXR2_MCASP			(0x00000000u)
+#define OMAPL_MCASP_PFUNC_AXR2_GPIO				(0x00000001u)
+
+#define OMAPL_MCASP_PFUNC_AXR1_MASK				(0x00000002u)
+#define OMAPL_MCASP_PFUNC_AXR1_SHIFT			(0x00000001u)
+#define OMAPL_MCASP_PFUNC_AXR1_RESETVAL			(0x00000000u)
+/* AXR1 Tokens */
+#define OMAPL_MCASP_PFUNC_AXR1_MCASP			(0x00000000u)
+#define OMAPL_MCASP_PFUNC_AXR1_GPIO				(0x00000001u)
+
+#define OMAPL_MCASP_PFUNC_AXR0_MASK				(0x00000001u)
+#define OMAPL_MCASP_PFUNC_AXR0_SHIFT			(0x00000000u)
+#define OMAPL_MCASP_PFUNC_AXR0_RESETVAL			(0x00000000u)
+/* AXR0 Tokens */
+#define OMAPL_MCASP_PFUNC_AXR0_MCASP			(0x00000000u)
+#define OMAPL_MCASP_PFUNC_AXR0_GPIO				(0x00000001u)
+#define OMAPL_MCASP_PFUNC_RESETVAL				(0x00000000u)
+
+#define OMAPL_MCASP_PDIR_AFSR_MASK				(0x80000000u)
+#define OMAPL_MCASP_PDIR_AFSR_SHIFT				(0x0000001Fu)
+#define OMAPL_MCASP_PDIR_AFSR_RESETVAL			(0x00000000u)
+/* AFSR Tokens */
+#define OMAPL_MCASP_PDIR_AFSR_INPUT				(0x00000000u)
+#define OMAPL_MCASP_PDIR_AFSR_OUTPUT			(0x00000001u)
+
+#define OMAPL_MCASP_PDIR_AHCLKR_MASK			(0x40000000u)
+#define OMAPL_MCASP_PDIR_AHCLKR_SHIFT			(0x0000001Eu)
+#define OMAPL_MCASP_PDIR_AHCLKR_RESETVAL		(0x00000000u)
+/* AHCLKR Tokens */
+#define OMAPL_MCASP_PDIR_AHCLKR_INPUT			(0x00000000u)
+#define OMAPL_MCASP_PDIR_AHCLKR_OUTPUT			(0x00000001u)
+
+#define OMAPL_MCASP_PDIR_ACLKR_MASK				(0x20000000u)
+#define OMAPL_MCASP_PDIR_ACLKR_SHIFT			(0x0000001Du)
+#define OMAPL_MCASP_PDIR_ACLKR_RESETVAL			(0x00000000u)
+/* ACLKR Tokens */
+#define OMAPL_MCASP_PDIR_ACLKR_INPUT			(0x00000000u)
+#define OMAPL_MCASP_PDIR_ACLKR_OUTPUT			(0x00000001u)
+
+#define OMAPL_MCASP_PDIR_AFSX_MASK				(0x10000000u)
+#define OMAPL_MCASP_PDIR_AFSX_SHIFT				(0x0000001Cu)
+#define OMAPL_MCASP_PDIR_AFSX_RESETVAL			(0x00000000u)
+/* AFSX Tokens */
+#define OMAPL_MCASP_PDIR_AFSX_INPUT				(0x00000000u)
+#define OMAPL_MCASP_PDIR_AFSX_OUTPUT			(0x00000001u)
+
+#define OMAPL_MCASP_PDIR_AHCLKX_MASK			(0x08000000u)
+#define OMAPL_MCASP_PDIR_AHCLKX_SHIFT			(0x0000001Bu)
+#define OMAPL_MCASP_PDIR_AHCLKX_RESETVAL		(0x00000000u)
+/* AHCLKX Tokens */
+#define OMAPL_MCASP_PDIR_AHCLKX_INPUT			(0x00000000u)
+#define OMAPL_MCASP_PDIR_AHCLKX_OUTPUT			(0x00000001u)
+
+#define OMAPL_MCASP_PDIR_ACLKX_MASK				(0x04000000u)
+#define OMAPL_MCASP_PDIR_ACLKX_SHIFT			(0x0000001Au)
+#define OMAPL_MCASP_PDIR_ACLKX_RESETVAL			(0x00000000u)
+/* ACLKX Tokens */
+#define OMAPL_MCASP_PDIR_ACLKX_INPUT			(0x00000000u)
+#define OMAPL_MCASP_PDIR_ACLKX_OUTPUT			(0x00000001u)
+
+#define OMAPL_MCASP_PDIR_AMUTE_MASK				(0x02000000u)
+#define OMAPL_MCASP_PDIR_AMUTE_SHIFT			(0x00000019u)
+#define OMAPL_MCASP_PDIR_AMUTE_RESETVAL			(0x00000000u)
+/* AMUTE Tokens */
+#define OMAPL_MCASP_PDIR_AMUTE_INPUT			(0x00000000u)
+#define OMAPL_MCASP_PDIR_AMUTE_OUTPUT			(0x00000001u)
+
+#define OMAPL_MCASP_PDIR_AXR15_MASK				(0x00008000u)
+#define OMAPL_MCASP_PDIR_AXR15_SHIFT			(0x0000000Fu)
+#define OMAPL_MCASP_PDIR_AXR15_RESETVAL			(0x00000000u)
+#define OMAPL_MCASP_PDIR_AXR15_INPUT			(0x00000000u)
+#define OMAPL_MCASP_PDIR_AXR15_OUTPUT			(0x00000001u)
+
+#define OMAPL_MCASP_PDIR_AXR14_MASK				(0x00004000u)
+#define OMAPL_MCASP_PDIR_AXR14_SHIFT			(0x0000000Eu)
+#define OMAPL_MCASP_PDIR_AXR14_RESETVAL			(0x00000000u)
+#define OMAPL_MCASP_PDIR_AXR14_INPUT			(0x00000000u)
+#define OMAPL_MCASP_PDIR_AXR14_OUTPUT			(0x00000001u)
+
+#define OMAPL_MCASP_PDIR_AXR13_MASK				(0x00002000u)
+#define OMAPL_MCASP_PDIR_AXR13_SHIFT			(0x0000000Du)
+#define OMAPL_MCASP_PDIR_AXR13_RESETVAL			(0x00000000u)
+#define OMAPL_MCASP_PDIR_AXR13_INPUT			(0x00000000u)
+#define OMAPL_MCASP_PDIR_AXR13_OUTPUT			(0x00000001u)
+
+#define OMAPL_MCASP_PDIR_AXR12_MASK				(0x00001000u)
+#define OMAPL_MCASP_PDIR_AXR12_SHIFT			(0x0000000Cu)
+#define OMAPL_MCASP_PDIR_AXR12_RESETVAL			(0x00000000u)
+#define OMAPL_MCASP_PDIR_AXR12_INPUT			(0x00000000u)
+#define OMAPL_MCASP_PDIR_AXR12_OUTPUT			(0x00000001u)
+
+#define OMAPL_MCASP_PDIR_AXR11_MASK				(0x00000800u)
+#define OMAPL_MCASP_PDIR_AXR11_SHIFT			(0x0000000Bu)
+#define OMAPL_MCASP_PDIR_AXR11_RESETVAL			(0x00000000u)
+#define OMAPL_MCASP_PDIR_AXR11_INPUT			(0x00000000u)
+#define OMAPL_MCASP_PDIR_AXR11_OUTPUT			(0x00000001u)
+
+#define OMAPL_MCASP_PDIR_AXR10_MASK				(0x00000400u)
+#define OMAPL_MCASP_PDIR_AXR10_SHIFT			(0x0000000Au)
+#define OMAPL_MCASP_PDIR_AXR10_RESETVAL			(0x00000000u)
+#define OMAPL_MCASP_PDIR_AXR10_INPUT			(0x00000000u)
+#define OMAPL_MCASP_PDIR_AXR10_OUTPUT			(0x00000001u)
+#define OMAPL_MCASP_PDIR_AXR9_MASK				(0x00000200u)
+#define OMAPL_MCASP_PDIR_AXR9_SHIFT				(0x00000009u)
+#define OMAPL_MCASP_PDIR_AXR9_RESETVAL			(0x00000000u)
+/* AXR9 Tokens */
+#define OMAPL_MCASP_PDIR_AXR9_INPUT				(0x00000000u)
+#define OMAPL_MCASP_PDIR_AXR9_OUTPUT			(0x00000001u)
+
+#define OMAPL_MCASP_PDIR_AXR8_MASK				(0x00000100u)
+#define OMAPL_MCASP_PDIR_AXR8_SHIFT				(0x00000008u)
+#define OMAPL_MCASP_PDIR_AXR8_RESETVAL			(0x00000000u)
+/* AXR8 Tokens */
+#define OMAPL_MCASP_PDIR_AXR8_INPUT				(0x00000000u)
+#define OMAPL_MCASP_PDIR_AXR8_OUTPUT			(0x00000001u)
+
+#define OMAPL_MCASP_PDIR_AXR7_MASK				(0x00000080u)
+#define OMAPL_MCASP_PDIR_AXR7_SHIFT				(0x00000007u)
+#define OMAPL_MCASP_PDIR_AXR7_RESETVAL			(0x00000000u)
+/*----AXR7 Tokens----*/
+#define OMAPL_MCASP_PDIR_AXR7_INPUT				(0x00000000u)
+#define OMAPL_MCASP_PDIR_AXR7_OUTPUT			(0x00000001u)
+
+#define OMAPL_MCASP_PDIR_AXR6_MASK				(0x00000040u)
+#define OMAPL_MCASP_PDIR_AXR6_SHIFT				(0x00000006u)
+#define OMAPL_MCASP_PDIR_AXR6_RESETVAL			(0x00000000u)
+/*----AXR6 Tokens----*/
+#define OMAPL_MCASP_PDIR_AXR6_INPUT				(0x00000000u)
+#define OMAPL_MCASP_PDIR_AXR6_OUTPUT			(0x00000001u)
+
+#define OMAPL_MCASP_PDIR_AXR5_MASK				(0x00000020u)
+#define OMAPL_MCASP_PDIR_AXR5_SHIFT				(0x00000005u)
+#define OMAPL_MCASP_PDIR_AXR5_RESETVAL			(0x00000000u)
+/*----AXR5 Tokens----*/
+#define OMAPL_MCASP_PDIR_AXR5_INPUT				(0x00000000u)
+#define OMAPL_MCASP_PDIR_AXR5_OUTPUT			(0x00000001u)
+
+#define OMAPL_MCASP_PDIR_AXR4_MASK				(0x00000010u)
+#define OMAPL_MCASP_PDIR_AXR4_SHIFT				(0x00000004u)
+#define OMAPL_MCASP_PDIR_AXR4_RESETVAL			(0x00000000u)
+/*----AXR4 Tokens----*/
+#define OMAPL_MCASP_PDIR_AXR4_INPUT				(0x00000000u)
+#define OMAPL_MCASP_PDIR_AXR4_OUTPUT			(0x00000001u)
+
+#define OMAPL_MCASP_PDIR_AXR3_MASK				(0x00000008u)
+#define OMAPL_MCASP_PDIR_AXR3_SHIFT				(0x00000003u)
+#define OMAPL_MCASP_PDIR_AXR3_RESETVAL			(0x00000000u)
+/*----AXR3 Tokens----*/
+#define OMAPL_MCASP_PDIR_AXR3_INPUT				(0x00000000u)
+#define OMAPL_MCASP_PDIR_AXR3_OUTPUT			(0x00000001u)
+
+#define OMAPL_MCASP_PDIR_AXR2_MASK				(0x00000004u)
+#define OMAPL_MCASP_PDIR_AXR2_SHIFT				(0x00000002u)
+#define OMAPL_MCASP_PDIR_AXR2_RESETVAL			(0x00000000u)
+/*----AXR2 Tokens----*/
+#define OMAPL_MCASP_PDIR_AXR2_INPUT				(0x00000000u)
+#define OMAPL_MCASP_PDIR_AXR2_OUTPUT			(0x00000001u)
+
+#define OMAPL_MCASP_PDIR_AXR1_MASK				(0x00000002u)
+#define OMAPL_MCASP_PDIR_AXR1_SHIFT				(0x00000001u)
+#define OMAPL_MCASP_PDIR_AXR1_RESETVAL			(0x00000000u)
+/*----AXR1 Tokens----*/
+#define OMAPL_MCASP_PDIR_AXR1_INPUT				(0x00000000u)
+#define OMAPL_MCASP_PDIR_AXR1_OUTPUT			(0x00000001u)
+
+#define OMAPL_MCASP_PDIR_AXR0_MASK				(0x00000001u)
+#define OMAPL_MCASP_PDIR_AXR0_SHIFT				(0x00000000u)
+#define OMAPL_MCASP_PDIR_AXR0_RESETVAL			(0x00000000u)
+/*----AXR0 Tokens----*/
+#define OMAPL_MCASP_PDIR_AXR0_INPUT				(0x00000000u)
+#define OMAPL_MCASP_PDIR_AXR0_OUTPUT			(0x00000001u)
+
+#define OMAPL_MCASP_PDIR_RESETVAL				(0x00000000u)
+
+#define OMAPL_MCASP_ACLKXCTL_CLKXP_MASK			(0x00000080u)
+#define OMAPL_MCASP_ACLKXCTL_CLKXP_SHIFT		(0x00000007u)
+#define OMAPL_MCASP_ACLKXCTL_CLKXP_RESETVAL		(0x00000000u)
+/*----CLKXP Tokens----*/
+#define OMAPL_MCASP_ACLKXCTL_CLKXP_RISINGEDGE	(0x00000000u)
+#define OMAPL_MCASP_ACLKXCTL_CLKXP_FALLINGEDGE	(0x00000001u)
+
+#define OMAPL_MCASP_ACLKXCTL_ASYNC_MASK			(0x00000040u)
+#define OMAPL_MCASP_ACLKXCTL_ASYNC_SHIFT		(0x00000006u)
+#define OMAPL_MCASP_ACLKXCTL_ASYNC_RESETVAL		(0x00000001u)
+/*----ASYNC Tokens----*/
+#define OMAPL_MCASP_ACLKXCTL_ASYNC_SYNC			(0x00000000u)
+#define OMAPL_MCASP_ACLKXCTL_ASYNC_ASYNC		(0x00000001u)
+
+#define OMAPL_MCASP_ACLKXCTL_CLKXM_MASK			(0x00000020u)
+#define OMAPL_MCASP_ACLKXCTL_CLKXM_SHIFT		(0x00000005u)
+#define OMAPL_MCASP_ACLKXCTL_CLKXM_RESETVAL		(0x00000001u)
+/*----CLKXM Tokens----*/
+#define OMAPL_MCASP_ACLKXCTL_CLKXM_EXTERNAL		(0x00000000u)
+#define OMAPL_MCASP_ACLKXCTL_CLKXM_INTERNAL		(0x00000001u)
+
+#define OMAPL_MCASP_ACLKXCTL_CLKXDIV_MASK		(0x0000001Fu)
+#define OMAPL_MCASP_ACLKXCTL_CLKXDIV_SHIFT		(0x00000000u)
+#define OMAPL_MCASP_ACLKXCTL_CLKXDIV_RESETVAL	(0x00000000u)
+
+#define OMAPL_MCASP_ACLKXCTL_RESETVAL			(0x00000060u)
+
+/* AHCLKXCTL */
+#define OMAPL_MCASP_AHCLKXCTL_HCLKXM_MASK		(0x00008000u)
+#define OMAPL_MCASP_AHCLKXCTL_HCLKXM_SHIFT		(0x0000000Fu)
+#define OMAPL_MCASP_AHCLKXCTL_HCLKXM_RESETVAL	(0x00000001u)
+/*----HCLKXM Tokens----*/
+#define OMAPL_MCASP_AHCLKXCTL_HCLKXM_EXTERNAL	(0x00000000u)
+#define OMAPL_MCASP_AHCLKXCTL_HCLKXM_INTERNAL	(0x00000001u)
+
+#define OMAPL_MCASP_AHCLKXCTL_HCLKXP_MASK		(0x00004000u)
+#define OMAPL_MCASP_AHCLKXCTL_HCLKXP_SHIFT		(0x0000000Eu)
+#define OMAPL_MCASP_AHCLKXCTL_HCLKXP_RESETVAL	(0x00000000u)
+/*----HCLKXP Tokens----*/
+#define OMAPL_MCASP_AHCLKXCTL_HCLKXP_NOTINVERTED	(0x00000000u)
+#define OMAPL_MCASP_AHCLKXCTL_HCLKXP_INVERTED	(0x00000001u)
+
+#define OMAPL_MCASP_AHCLKXCTL_HCLKXDIV_MASK		(0x00000FFFu)
+#define OMAPL_MCASP_AHCLKXCTL_HCLKXDIV_SHIFT	(0x00000000u)
+#define OMAPL_MCASP_AHCLKXCTL_HCLKXDIV_RESETVAL	(0x00000000u)
+
+#define OMAPL_MCASP_AHCLKXCTL_RESETVAL			(0x00008000u)
+
+#endif
diff --git a/arch/arm/mach-davinci/include/mach/pru/omapl_pru.h b/arch/arm/mach-davinci/include/mach/pru/omapl_pru.h
new file mode 100644
index 0000000..52b10e8
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/pru/omapl_pru.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2010 Texas Instruments Incorporated
+ * Author: Jitendra Kumar <jitendra@mistralsolutions.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as  published by the
+ * Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ */
+
+#ifndef _OMAPL_PRU_H_
+#define _OMAPL_PRU_H_
+
+#define OMAPL_PRU_FMK(PER_REG_FIELD, val)							\
+	(((val) << OMAPL_##PER_REG_FIELD##_SHIFT) & OMAPL_##PER_REG_FIELD##_MASK)
+
+#define OMAPL_PRU_FEXT(reg, PER_REG_FIELD)							\
+	(((reg) & OMAPL_##PER_REG_FIELD##_MASK) >> OMAPL_##PER_REG_FIELD##_SHIFT)
+
+#define OMAPL_PRU_FINS(reg, PER_REG_FIELD, val)						\
+	((reg) = ((reg) & ~OMAPL_##PER_REG_FIELD##_MASK)				\
+	| OMAPL_PRU_FMK(PER_REG_FIELD, val))
+
+#define OMAPL_PRU_FMKT(PER_REG_FIELD, TOKEN)						\
+	OMAPL_PRU_FMK(PER_REG_FIELD, OMAPL_##PER_REG_FIELD##_##TOKEN)
+
+#define OMAPL_PRU_FINST(reg, PER_REG_FIELD, TOKEN)					\
+	OMAPL_PRU_FINS((reg), PER_REG_FIELD, OMAPL_##PER_REG_FIELD##_##TOKEN)
+
+#define OMAPL_PRU_FMKR(msb, lsb, val)								\
+	(((val) & ((1 << ((msb) - (lsb) + 1)) - 1)) << (lsb))
+
+#define OMAPL_PRU_FEXTR(reg, msb, lsb)								\
+	(((reg) >> (lsb)) & ((1 << ((msb) - (lsb) + 1)) - 1))
+
+#define OMAPL_PRU_FINSR(reg, msb, lsb, val)							\
+	((reg) = ((reg) & ~(((1 << ((msb) - (lsb) + 1)) - 1) << (lsb)))	\
+	| OMAPL_PRU_FMKR(msb, lsb, val))
+
+#endif				/* _OMAPL_PRU_H_ */
diff --git a/arch/arm/mach-davinci/include/mach/pru/omapl_prucore.h b/arch/arm/mach-davinci/include/mach/pru/omapl_prucore.h
new file mode 100644
index 0000000..cf43b1f
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/pru/omapl_prucore.h
@@ -0,0 +1,137 @@
+/*
+ * Copyright (C) 2010 Texas Instruments Incorporated
+ * Author: Jitendra Kumar <jitendra@mistralsolutions.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as  published by the
+ * Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ */
+
+#ifndef _OMAPL_PRUCORE_H_
+#define _OMAPL_PRUCORE_H_
+
+#include <linux/types.h>
+#include <mach/pru/omapl_pru.h>
+
+#define OMAPL_PRUCORE_0		(0)
+#define OMAPL_PRUCORE_1		(1)
+
+#define OMAPL_PRUCORE_CONTROL_PCRESETVAL_MASK			(0xFFFF0000u)
+#define OMAPL_PRUCORE_CONTROL_PCRESETVAL_SHIFT			(0x00000010u)
+#define OMAPL_PRUCORE_CONTROL_PCRESETVAL_RESETVAL		(0x00000000u)
+#define OMAPL_PRUCORE_CONTROL_RUNSTATE_MASK				(0x00008000u)
+#define OMAPL_PRUCORE_CONTROL_RUNSTATE_SHIFT			(0x0000000Fu)
+#define OMAPL_PRUCORE_CONTROL_RUNSTATE_RESETVAL			(0x00000000u)
+#define OMAPL_PRUCORE_CONTROL_RUNSTATE_HALT				(0x00000000u)
+#define OMAPL_PRUCORE_CONTROL_RUNSTATE_RUN				(0x00000001u)
+#define OMAPL_PRUCORE_CONTROL_SINGLESTEP_MASK			(0x00000100u)
+#define OMAPL_PRUCORE_CONTROL_SINGLESTEP_SHIFT			(0x00000008u)
+#define OMAPL_PRUCORE_CONTROL_SINGLESTEP_RESETVAL		(0x00000000u)
+#define OMAPL_PRUCORE_CONTROL_SINGLESTEP_FREERUN		(0x00000000u)
+#define OMAPL_PRUCORE_CONTROL_SINGLESTEP_SINGLE			(0x00000001u)
+#define OMAPL_PRUCORE_CONTROL_COUNTENABLE_MASK			(0x00000008u)
+#define OMAPL_PRUCORE_CONTROL_COUNTENABLE_SHIFT			(0x00000003u)
+#define OMAPL_PRUCORE_CONTROL_COUNTENABLE_RESETVAL		(0x00000000u)
+#define OMAPL_PRUCORE_CONTROL_COUNTENABLE_DISABLE		(0x00000000u)
+#define OMAPL_PRUCORE_CONTROL_COUNTENABLE_ENABLE		(0x00000001u)
+#define OMAPL_PRUCORE_CONTROL_SLEEPING_MASK				(0x00000004u)
+#define OMAPL_PRUCORE_CONTROL_SLEEPING_SHIFT			(0x00000002u)
+#define OMAPL_PRUCORE_CONTROL_SLEEPING_RESETVAL			(0x00000000u)
+#define OMAPL_PRUCORE_CONTROL_SLEEPING_NOTASLEEP		(0x00000000u)
+#define OMAPL_PRUCORE_CONTROL_SLEEPING_ASLEEP			(0x00000001u)
+#define OMAPL_PRUCORE_CONTROL_ENABLE_MASK				(0x00000002u)
+#define OMAPL_PRUCORE_CONTROL_ENABLE_SHIFT				(0x00000001u)
+#define OMAPL_PRUCORE_CONTROL_ENABLE_RESETVAL			(0x00000000u)
+#define OMAPL_PRUCORE_CONTROL_ENABLE_DISABLE			(0x00000000u)
+#define OMAPL_PRUCORE_CONTROL_ENABLE_ENABLE				(0x00000001u)
+#define OMAPL_PRUCORE_CONTROL_SOFTRESET_MASK			(0x00000001u)
+#define OMAPL_PRUCORE_CONTROL_SOFTRESET_SHIFT			(0x00000000u)
+#define OMAPL_PRUCORE_CONTROL_SOFTRESET_RESETVAL		(0x00000000u)
+#define OMAPL_PRUCORE_CONTROL_SOFTRESET_RESET			(0x00000000u)
+#define OMAPL_PRUCORE_CONTROL_SOFTRESET_OUT_OF_RESET	(0x00000001u)
+#define OMAPL_PRUCORE_CONTROL_RESETVAL					(0x00000000u)
+
+typedef struct {
+	volatile u32 CONTROL;
+	volatile u32 STATUS;
+	volatile u32 WAKEUP;
+	volatile u32 CYCLECNT;
+	volatile u32 STALLCNT;
+	volatile u8 RSVD0[12];
+	volatile u32 CONTABBLKIDX0;
+	volatile u32 CONTABBLKIDX1;
+	volatile u32 CONTABPROPTR0;
+	volatile u32 CONTABPROPTR1;
+	volatile u8 RSVD1[976];
+	volatile u32 INTGPR0;
+	volatile u32 INTGPR1;
+	volatile u32 INTGPR2;
+	volatile u32 INTGPR3;
+	volatile u32 INTGPR4;
+	volatile u32 INTGPR5;
+	volatile u32 INTGPR6;
+	volatile u32 INTGPR7;
+	volatile u32 INTGPR8;
+	volatile u32 INTGPR9;
+	volatile u32 INTGPR10;
+	volatile u32 INTGPR11;
+	volatile u32 INTGPR12;
+	volatile u32 INTGPR13;
+	volatile u32 INTGPR14;
+	volatile u32 INTGPR15;
+	volatile u32 INTGPR16;
+	volatile u32 INTGPR17;
+	volatile u32 INTGPR18;
+	volatile u32 INTGPR19;
+	volatile u32 INTGPR20;
+	volatile u32 INTGPR21;
+	volatile u32 INTGPR22;
+	volatile u32 INTGPR23;
+	volatile u32 INTGPR24;
+	volatile u32 INTGPR25;
+	volatile u32 INTGPR26;
+	volatile u32 INTGPR27;
+	volatile u32 INTGPR28;
+	volatile u32 INTGPR29;
+	volatile u32 INTGPR30;
+	volatile u32 INTGPR31;
+	volatile u32 INTCTER0;
+	volatile u32 INTCTER1;
+	volatile u32 INTCTER2;
+	volatile u32 INTCTER3;
+	volatile u32 INTCTER4;
+	volatile u32 INTCTER5;
+	volatile u32 INTCTER6;
+	volatile u32 INTCTER7;
+	volatile u32 INTCTER8;
+	volatile u32 INTCTER9;
+	volatile u32 INTCTER10;
+	volatile u32 INTCTER11;
+	volatile u32 INTCTER12;
+	volatile u32 INTCTER13;
+	volatile u32 INTCTER14;
+	volatile u32 INTCTER15;
+	volatile u32 INTCTER16;
+	volatile u32 INTCTER17;
+	volatile u32 INTCTER18;
+	volatile u32 INTCTER19;
+	volatile u32 INTCTER20;
+	volatile u32 INTCTER21;
+	volatile u32 INTCTER22;
+	volatile u32 INTCTER23;
+	volatile u32 INTCTER24;
+	volatile u32 INTCTER25;
+	volatile u32 INTCTER26;
+	volatile u32 INTCTER27;
+	volatile u32 INTCTER28;
+	volatile u32 INTCTER29;
+	volatile u32 INTCTER30;
+	volatile u32 INTCTER31;
+} OMAPL_PrucoreRegs, *OMAPL_PrucoreRegsOvly;
+
+#endif
diff --git a/arch/arm/mach-davinci/include/mach/pru/pru.h b/arch/arm/mach-davinci/include/mach/pru/pru.h
new file mode 100644
index 0000000..377716d
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/pru/pru.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (C) 2010 Texas Instruments Incorporated
+ * Author: Jitendra Kumar <jitendra@mistralsolutions.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as  published by the
+ * Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ */
+
+#ifndef _PRU_H_
+#define _PRU_H_
+
+#include <linux/types.h>
+#include "omapl_prucore.h"
+
+#define PRU_NUM0		OMAPL_PRUCORE_0
+#define PRU_NUM1		OMAPL_PRUCORE_1
+
+#define PRU_PRU0_BASE_ADDRESS			0
+#define PRU_INTC_BASE_ADDRESS			(PRU_PRU0_BASE_ADDRESS + 0x4000)
+#define PRU_INTC_GLBLEN					(PRU_INTC_BASE_ADDRESS + 0x10)
+#define PRU_INTC_GLBLNSTLVL				(PRU_INTC_BASE_ADDRESS + 0x1C)
+#define PRU_INTC_STATIDXSET				(PRU_INTC_BASE_ADDRESS + 0x20)
+#define PRU_INTC_STATIDXCLR				(PRU_INTC_BASE_ADDRESS + 0x24)
+#define PRU_INTC_ENIDXSET				(PRU_INTC_BASE_ADDRESS + 0x28)
+#define PRU_INTC_ENIDXCLR				(PRU_INTC_BASE_ADDRESS + 0x2C)
+#define PRU_INTC_HSTINTENIDXSET			(PRU_INTC_BASE_ADDRESS + 0x34)
+#define PRU_INTC_HSTINTENIDXCLR			(PRU_INTC_BASE_ADDRESS + 0x38)
+#define PRU_INTC_GLBLPRIIDX				(PRU_INTC_BASE_ADDRESS + 0x80)
+#define PRU_INTC_STATSETINT0			(PRU_INTC_BASE_ADDRESS + 0x200)
+#define PRU_INTC_STATSETINT1			(PRU_INTC_BASE_ADDRESS + 0x204)
+#define PRU_INTC_STATCLRINT0			(PRU_INTC_BASE_ADDRESS + 0x280)
+#define PRU_INTC_STATCLRINT1			(PRU_INTC_BASE_ADDRESS + 0x284)
+#define PRU_INTC_ENABLESET0				(PRU_INTC_BASE_ADDRESS + 0x300)
+#define PRU_INTC_ENABLESET1				(PRU_INTC_BASE_ADDRESS + 0x304)
+#define PRU_INTC_ENABLECLR0				(PRU_INTC_BASE_ADDRESS + 0x380)
+#define PRU_INTC_ENABLECLR1				(PRU_INTC_BASE_ADDRESS + 0x384)
+#define PRU_INTC_CHANMAP0				(PRU_INTC_BASE_ADDRESS + 0x400)
+#define PRU_INTC_CHANMAP1				(PRU_INTC_BASE_ADDRESS + 0x404)
+#define PRU_INTC_CHANMAP2				(PRU_INTC_BASE_ADDRESS + 0x408)
+#define PRU_INTC_CHANMAP3				(PRU_INTC_BASE_ADDRESS + 0x40C)
+#define PRU_INTC_CHANMAP4				(PRU_INTC_BASE_ADDRESS + 0x410)
+#define PRU_INTC_CHANMAP5				(PRU_INTC_BASE_ADDRESS + 0x414)
+#define PRU_INTC_CHANMAP6				(PRU_INTC_BASE_ADDRESS + 0x418)
+#define PRU_INTC_CHANMAP7				(PRU_INTC_BASE_ADDRESS + 0x41C)
+#define PRU_INTC_CHANMAP8				(PRU_INTC_BASE_ADDRESS + 0x420)
+#define PRU_INTC_CHANMAP9				(PRU_INTC_BASE_ADDRESS + 0x424)
+#define PRU_INTC_CHANMAP10				(PRU_INTC_BASE_ADDRESS + 0x428)
+#define PRU_INTC_CHANMAP11				(PRU_INTC_BASE_ADDRESS + 0x42C)
+#define PRU_INTC_CHANMAP12				(PRU_INTC_BASE_ADDRESS + 0x430)
+#define PRU_INTC_CHANMAP13				(PRU_INTC_BASE_ADDRESS + 0x434)
+#define PRU_INTC_CHANMAP14				(PRU_INTC_BASE_ADDRESS + 0x438)
+#define PRU_INTC_CHANMAP15				(PRU_INTC_BASE_ADDRESS + 0x43C)
+#define PRU_INTC_HOSTMAP0				(PRU_INTC_BASE_ADDRESS + 0x800)
+#define PRU_INTC_HOSTMAP1				(PRU_INTC_BASE_ADDRESS + 0x804)
+#define PRU_INTC_HOSTMAP2				(PRU_INTC_BASE_ADDRESS + 0x808)
+#define PRU_INTC_POLARITY0				(PRU_INTC_BASE_ADDRESS + 0xD00)
+#define PRU_INTC_POLARITY1				(PRU_INTC_BASE_ADDRESS + 0xD04)
+#define PRU_INTC_TYPE0					(PRU_INTC_BASE_ADDRESS + 0xD80)
+#define PRU_INTC_TYPE1					(PRU_INTC_BASE_ADDRESS + 0xD84)
+#define PRU_INTC_HOSTINTEN				(PRU_INTC_BASE_ADDRESS + 0x1500)
+#define PRU_INTC_HOSTINTLVL_MAX			9
+
+typedef struct arm_pru_iomap {
+	void *pru_io_addr;
+	void *mcasp_io_addr;
+	void *pFifoBufferPhysBase;
+	void *pFifoBufferVirtBase;
+	u32  pru_clk_freq;
+} arm_pru_iomap;
+
+u32 pru_enable(u8 pruNum, arm_pru_iomap *pru_arm_iomap);
+
+u32 pru_load(u8 pruNum, u32 *pruCode, u32 codeSizeInWords,
+			arm_pru_iomap *pru_arm_iomap);
+
+u32 pru_run(u8 pruNum, arm_pru_iomap *pru_arm_iomap);
+
+u32 pru_waitForHalt(u8 pruNum, s32 timeout, arm_pru_iomap *pru_arm_iomap);
+
+u32 pru_disable(arm_pru_iomap *pru_arm_iomap);
+
+s16 pru_ram_write_data(u32 u32offset, u8 *pu8datatowrite,
+			u16 u16wordstowrite, arm_pru_iomap *pru_arm_iomap);
+
+s16 pru_ram_read_data(u32 u32offset, u8 *pu8datatoread,
+			u16 u16wordstoread, arm_pru_iomap *pru_arm_iomap);
+
+s16 pru_ram_read_data_4byte(u32 u32offset, u32 *pu32datatoread,
+			s16 s16wordstoread);
+
+s16 pru_ram_write_data_4byte(u32 u32offset, u32 *pu32datatoread,
+			s16 s16wordstoread);
+
+#endif	/* End _PRU_H_ */
diff --git a/arch/arm/mach-davinci/pru.c b/arch/arm/mach-davinci/pru.c
new file mode 100644
index 0000000..0cd2561
--- /dev/null
+++ b/arch/arm/mach-davinci/pru.c
@@ -0,0 +1,237 @@
+/*
+ * Copyright (C) 2010 Texas Instruments Incorporated
+ * Author: Jitendra Kumar <jitendra@mistralsolutions.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as  published by the
+ * Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ */
+
+#include <linux/types.h>
+#include <linux/module.h>
+#include <asm-generic/errno-base.h>
+#include <mach/pru/omapl_pru.h>
+#include <mach/pru/omapl_prucore.h>
+#include <mach/pru/pru.h>
+
+u32 pru_disable(arm_pru_iomap *pru_arm_iomap)
+{
+	OMAPL_PrucoreRegsOvly hPru;
+
+	/* Disable PRU0  */
+	hPru = (OMAPL_PrucoreRegsOvly)
+		((u32) pru_arm_iomap->pru_io_addr + 0x7000);
+	OMAPL_PRU_FINST(hPru->CONTROL, PRUCORE_CONTROL_COUNTENABLE, DISABLE);
+	OMAPL_PRU_FINST(hPru->CONTROL, PRUCORE_CONTROL_ENABLE, DISABLE);
+
+	/* Reset PRU0 */
+	hPru->CONTROL = OMAPL_PRUCORE_CONTROL_RESETVAL;
+
+	/* Disable PRU1 */
+	hPru = (OMAPL_PrucoreRegsOvly)
+		((u32) pru_arm_iomap->pru_io_addr + 0x7800);
+	OMAPL_PRU_FINST(hPru->CONTROL, PRUCORE_CONTROL_COUNTENABLE, DISABLE);
+	OMAPL_PRU_FINST(hPru->CONTROL, PRUCORE_CONTROL_ENABLE, DISABLE);
+
+	/* Reset PRU1 */
+	hPru->CONTROL = OMAPL_PRUCORE_CONTROL_RESETVAL;
+
+	return 0;
+}
+EXPORT_SYMBOL(pru_disable);
+
+u32 pru_enable(u8 pruNum, arm_pru_iomap *pru_arm_iomap)
+{
+	OMAPL_PrucoreRegsOvly hPru;
+
+	if (pruNum == OMAPL_PRUCORE_0) {
+		/* Reset PRU0 */
+		hPru = (OMAPL_PrucoreRegsOvly)
+			((u32) pru_arm_iomap->pru_io_addr + 0x7000);
+		hPru->CONTROL = OMAPL_PRUCORE_CONTROL_RESETVAL;
+	} else if (pruNum == OMAPL_PRUCORE_1) {
+		/* Reset PRU1  */
+		hPru = (OMAPL_PrucoreRegsOvly)
+			((u32) pru_arm_iomap->pru_io_addr + 0x7800);
+		hPru->CONTROL = OMAPL_PRUCORE_CONTROL_RESETVAL;
+	}
+	return 0;
+}
+EXPORT_SYMBOL(pru_enable);
+
+/* Load the specified PRU with code */
+u32 pru_load(u8 pruNum, u32 *pruCode, u32 codeSizeInWords,
+	     arm_pru_iomap *pru_arm_iomap)
+{
+	u32 *pruIram;
+	u32 i;
+
+	if (pruNum == OMAPL_PRUCORE_0) {
+		pruIram = (u32 *) ((u32) pru_arm_iomap->pru_io_addr + 0x8000);
+	} else if (pruNum == OMAPL_PRUCORE_1) {
+		pruIram = (u32 *) ((u32) pru_arm_iomap->pru_io_addr + 0xc000);
+	} else {
+		return -EIO;
+	}
+
+	pru_enable(pruNum, pru_arm_iomap);
+
+	/* Copy dMAX code to its instruction RAM  */
+	for (i = 0; i < codeSizeInWords; i++) {
+		pruIram[i] = pruCode[i];
+	}
+	return 0;
+}
+EXPORT_SYMBOL(pru_load);
+
+u32 pru_run(u8 pruNum, arm_pru_iomap *pru_arm_iomap)
+{
+	OMAPL_PrucoreRegsOvly hPru;
+
+	if (pruNum == OMAPL_PRUCORE_0) {
+		/* OMAPL_PRUCORE_0_REGS; */
+		hPru = (OMAPL_PrucoreRegsOvly)
+			((u32) pru_arm_iomap->pru_io_addr + 0x7000);
+	} else if (pruNum == OMAPL_PRUCORE_1) {
+		/* OMAPL_PRUCORE_1_REGS; */
+		hPru = (OMAPL_PrucoreRegsOvly)
+			((u32) pru_arm_iomap->pru_io_addr + 0x7800);
+	} else {
+		return -EIO;
+	}
+
+	/* Enable dMAX, let it execute the code we just copied */
+	OMAPL_PRU_FINST(hPru->CONTROL, PRUCORE_CONTROL_COUNTENABLE, ENABLE);
+	OMAPL_PRU_FINST(hPru->CONTROL, PRUCORE_CONTROL_ENABLE, ENABLE);
+	return 0;
+}
+EXPORT_SYMBOL(pru_run);
+
+u32 pru_waitForHalt(u8 pruNum, s32 timeout, arm_pru_iomap *pru_arm_iomap)
+{
+	OMAPL_PrucoreRegsOvly hPru;
+
+	s32 cnt = timeout;
+
+	if (pruNum == OMAPL_PRUCORE_0) {
+		/* OMAPL_PRUCORE_0_REGS; */
+		hPru = (OMAPL_PrucoreRegsOvly)
+			((u32) pru_arm_iomap->pru_io_addr + 0x7000);
+	} else if (pruNum == OMAPL_PRUCORE_1) {
+		/* OMAPL_PRUCORE_1_REGS; */
+		hPru = (OMAPL_PrucoreRegsOvly)
+			((u32) pru_arm_iomap->pru_io_addr + 0x7800);
+	} else {
+		return -EIO;
+	}
+
+	while (OMAPL_PRU_FEXT(hPru->CONTROL, PRUCORE_CONTROL_RUNSTATE) ==
+	       OMAPL_PRUCORE_CONTROL_RUNSTATE_RUN) {
+		if (cnt > 0) {
+			cnt--;
+		}
+		if (cnt == 0) {
+			return -EBUSY;
+		}
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(pru_waitForHalt);
+
+/*
+ * u32offset			Offset of the data RAM where
+ *                      the data has to be written
+ * pu32datatowrite		Pointer to a buffer that holds
+ *                      the data to be written into RAM
+ * u16wordstowrite		Number of bytes to be written into that RAM
+ *
+ * return	SUCCESS or FAILURE
+ */
+s16 pru_ram_write_data(u32 u32offset, u8 *pu8datatowrite,
+		u16 u16bytestowrite, arm_pru_iomap *pru_arm_iomap)
+{
+	u8 *pu8addresstowrite;
+	u16 u16loop;
+	u32offset = (u32)pru_arm_iomap->pru_io_addr + u32offset;
+	pu8addresstowrite = (u8 *) (u32offset);
+
+	for (u16loop = 0; u16loop < u16bytestowrite; u16loop++)
+		*pu8addresstowrite++ = *pu8datatowrite++;
+	return 0;
+}
+EXPORT_SYMBOL(pru_ram_write_data);
+
+/*
+ * param   u32offset		Offset of the data RAM where the
+ *                          data has to be read
+ * param   pu8datatoread	Pointer to a buffer that would hold
+ *                          the data to be read from the RAM
+ * param   u16bytestoread	Number of bytes to be read from RAM
+ *
+ * return   SUCCESS or FAILURE
+ */
+s16 pru_ram_read_data(u32 u32offset, u8 *pu8datatoread,
+		u16 u16bytestoread, arm_pru_iomap *pru_arm_iomap)
+{
+	u8 *pu8addresstoread;
+	u16 u16loop;
+	u32offset = (u32)pru_arm_iomap->pru_io_addr + u32offset;
+	pu8addresstoread = (u8 *) (u32offset);
+
+	for (u16loop = 0; u16loop < u16bytestoread; u16loop++)
+		*pu8datatoread++ = *pu8addresstoread++;
+	return 0;
+}
+EXPORT_SYMBOL(pru_ram_read_data);
+
+/*
+ * param	u32offset			Offset of the data RAM where the
+ *                              data has to be written
+ * param	pu32datatowrite		Pointer to a buffer that holds the
+ *                              data to be written into RAM
+ * param	u16wordstowrite		Number of words to be written
+ *
+ * return   SUCCESS or FAILURE
+ */
+s16 pru_ram_write_data_4byte(u32 u32offset, u32 *pu32datatowrite,
+		s16 u16wordstowrite)
+{
+	u32 *pu32addresstowrite;
+	s16 u16loop;
+
+	pu32addresstowrite = (u32 *)(u32offset);
+
+	for (u16loop = 0; u16loop < u16wordstowrite; u16loop++)
+		*pu32addresstowrite++ = *pu32datatowrite++;
+	return 0;
+}
+EXPORT_SYMBOL(pru_ram_write_data_4byte);
+
+/*
+ * param	u32offset			Offset of the data RAM where the
+ *                              data has to be read
+ * param	pu32datatoread		Pointer to a buffer that would hold the
+ *                              data to be read from the RAM
+ * param	u16wordstoread		Number of words to be read from RAM
+ *
+ * return   SUCCESS or FAILURE
+ */
+s16 pru_ram_read_data_4byte(u32 u32offset, u32 *pu32datatoread,
+		s16 u16wordstoread)
+{
+	u32 *pu32addresstoread;
+	s16 u16loop;
+
+	pu32addresstoread = (u32 *)(u32offset);
+
+	for (u16loop = 0; u16loop < u16wordstoread; u16loop++)
+		*pu32datatoread++ = *pu32addresstoread++;
+	return 0;
+}
+EXPORT_SYMBOL(pru_ram_read_data_4byte);
