[RFC:,4/5] da850: SocketCAN compliant driver for TI's PRU CAN Lite Emulation.

Message ID	1294063467-22465-4-git-send-email-subhasish@mistralsolutions.com (mailing list archive)
State	Changes Requested
Headers	show Received: from comal.ext.ti.com (comal.ext.ti.com [198.47.26.152]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p03DuN7N029492 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for <patchwork-davinci@patchwork.kernel.org>; Mon, 3 Jan 2011 13:56:50 GMT DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=LN/ux5bSSu3SuJh4oXXbXimrvYyw9XlBflUtIegNuDlpVxaUgZmB2+sUk8jO1ZDmfI 9/Ocgbko4E0Nymj6LQaeoR0a8h+MH/ifeeHHvi5PbVpeCF5At4QQTGzpcGuGMh0dLXC0 NKvRh/03L21jUpsSgt1RqlG3SMicHTkVymB3k= From: Subhasish Ghosh <ghosh.subhasish@gmail.com> To: davinci-linux-open-source@linux.davincidsp.com Subject: [RFC: PATCH 4/5] da850: SocketCAN compliant driver for TI's PRU CAN Lite Emulation. Date: Mon, 3 Jan 2011 19:34:26 +0530 Message-Id: <1294063467-22465-4-git-send-email-subhasish@mistralsolutions.com> In-Reply-To: <1294063467-22465-1-git-send-email-subhasish@mistralsolutions.com> References: <1294063467-22465-1-git-send-email-subhasish@mistralsolutions.com> Cc: m-watkins@ti.com, sshtylyov@mvista.com, Subhasish <subhasish@mistralsolutions.com> Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: davinci-linux-open-source-bounces@linux.davincidsp.com Errors-To: davinci-linux-open-source-bounces@linux.davincidsp.com

diff --git a/drivers/net/can/omapl_pru/Kconfig b/drivers/net/can/omapl_pru/Kconfig new file mode 100644 index 0000000..604f7f8 --- /dev/null +++ b/drivers/net/can/omapl_pru/Kconfig @@ -0,0 +1,65 @@ +# +# CAN Lite Kernel Configuration +# +config CAN_TI_OMAPL_PRU + depends on CAN_DEV && ARCH_DAVINCI && ARCH_DAVINCI_DA850 + tristate "PRU based CAN emulation for OMAPL" + ---help--- + Enable this to emulate a CAN controller on the PRU of OMAPL. + If not sure, mark N + +config OMAPL_PRU_CANID_MBX0 + hex "CANID for mailbox 0" + depends on CAN_TI_OMAPL_PRU + default "0x123" + ---help--- + Enter the CANID for mailbox 0 + +config OMAPL_PRU_CANID_MBX1 + hex "CANID for mailbox 1" + depends on CAN_TI_OMAPL_PRU + default "0x123" + ---help--- + Enter the CANID for mailbox 1 + +config OMAPL_PRU_CANID_MBX2 + hex "CANID for mailbox 2" + depends on CAN_TI_OMAPL_PRU + default "0x123" + ---help--- + Enter the CANID for mailbox 2 + +config OMAPL_PRU_CANID_MBX3 + hex "CANID for mailbox 3" + depends on CAN_TI_OMAPL_PRU + default "0x123" + ---help--- + Enter the CANID for mailbox 3 + +config OMAPL_PRU_CANID_MBX4 + hex "CANID for mailbox 4" + depends on CAN_TI_OMAPL_PRU + default "0x123" + ---help--- + Enter the CANID for mailbox 4 + +config OMAPL_PRU_CANID_MBX5 + hex "CANID for mailbox 5" + depends on CAN_TI_OMAPL_PRU + default "0x123" + ---help--- + Enter the CANID for mailbox 5 + +config OMAPL_PRU_CANID_MBX6 + hex "CANID for mailbox 6" + depends on CAN_TI_OMAPL_PRU + default "0x123" + ---help--- + Enter the CANID for mailbox 6 + +config OMAPL_PRU_CANID_MBX7 + hex "CANID for mailbox 7" + depends on CAN_TI_OMAPL_PRU + default "0x123" + ---help--- + Enter the CANID for mailbox 7 diff --git a/drivers/net/can/omapl_pru/Makefile b/drivers/net/can/omapl_pru/Makefile new file mode 100644 index 0000000..54a4448 --- /dev/null +++ b/drivers/net/can/omapl_pru/Makefile @@ -0,0 +1,7 @@ +# +# Makefile for CAN Lite emulation +# +can_emu-objs := ti_omapl_pru_can.o \ + pru_can_api.o + +obj-$(CONFIG_CAN_TI_OMAPL_PRU) += can_emu.o diff --git a/drivers/net/can/omapl_pru/omapl_syscfg0_OMAPL138.h b/drivers/net/can/omapl_pru/omapl_syscfg0_OMAPL138.h new file mode 100644 index 0000000..7c4c8b8 --- /dev/null +++ b/drivers/net/can/omapl_pru/omapl_syscfg0_OMAPL138.h @@ -0,0 +1,132 @@ +/* + * Copyright (C) 2010 Texas Instruments Incorporated + * Author: Wilfred Felix + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind, + * whether express or implied; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#ifndef _OMAPLR_SYSCFG0_H_ +#define _OMAPLR_SYSCFG0_H_ + +#include <mach/pru/omapl_pru.h> +#include <linux/types.h> + +typedef struct { + volatile u32 REVID; + volatile u8 RSVD0[4]; + volatile u32 DIEIDR0; + volatile u32 DIEIDR1; + volatile u32 DIEIDR2; + volatile u32 DIEIDR3; + volatile u32 DEVIDR0; + volatile u8 RSVD1[4]; + volatile u32 BOOTCFG; + volatile u32 CHIPREVIDR; + volatile u8 RSVD2[16]; + volatile u32 KICK0R; + volatile u32 KICK1R; + volatile u32 HOST0CFG; + volatile u32 HOST1CFG; + volatile u8 RSVD3[152]; + volatile u32 IRAWSTAT; + volatile u32 IENSTAT; + volatile u32 IENSET; + volatile u32 IENCLR; + volatile u32 EOI; + volatile u32 FLTADDRR; + volatile u32 FLTSTAT; + volatile u8 RSVD4[20]; + volatile u32 MSTPRI0; + volatile u32 MSTPRI1; + volatile u32 MSTPRI2; + volatile u8 RSVD5[4]; + volatile u32 PINMUX0; + volatile u32 PINMUX1; + volatile u32 PINMUX2; + volatile u32 PINMUX3; + volatile u32 PINMUX4; + volatile u32 PINMUX5; + volatile u32 PINMUX6; + volatile u32 PINMUX7; + volatile u32 PINMUX8; + volatile u32 PINMUX9; + volatile u32 PINMUX10; + volatile u32 PINMUX11; + volatile u32 PINMUX12; + volatile u32 PINMUX13; + volatile u32 PINMUX14; + volatile u32 PINMUX15; + volatile u32 PINMUX16; + volatile u32 PINMUX17; + volatile u32 PINMUX18; + volatile u32 PINMUX19; + volatile u32 SUSPSRC; + volatile u32 CHIPSIG; + volatile u32 CHIPSIG_CLR; + volatile u32 CFGCHIP0; + volatile u32 CFGCHIP1; + volatile u32 CFGCHIP2; + volatile u32 CFGCHIP3; + volatile u32 CFGCHIP4; +} OMAPL_SyscfgRegs, *OMAPL_SyscfgRegsOvly; + + +#define OMAPL_SYSCFG_CFGCHIP3_RMII_SEL_MASK (0x00000100u) +#define OMAPL_SYSCFG_CFGCHIP3_RMII_SEL_SHIFT (0x00000008u) +#define OMAPL_SYSCFG_CFGCHIP3_RMII_SEL_RESETVAL (0x00000001u) +/*----RMII_SEL Tokens----*/ +#define OMAPL_SYSCFG_CFGCHIP3_RMII_SEL_MII (0x00000000u) +#define OMAPL_SYSCFG_CFGCHIP3_RMII_SEL_RMII (0x00000001u) + +#define OMAPL_SYSCFG_CFGCHIP3_UPP_TX_CLKSRC_MASK (0x00000040u) +#define OMAPL_SYSCFG_CFGCHIP3_UPP_TX_CLKSRC_SHIFT (0x00000006u) +#define OMAPL_SYSCFG_CFGCHIP3_UPP_TX_CLKSRC_RESETVAL (0x00000000u) +/*----UPP_TX_CLKSRC Tokens----*/ +#define OMAPL_SYSCFG_CFGCHIP3_UPP_TX_CLKSRC_ASYNC3 (0x00000000u) +#define OMAPL_SYSCFG_CFGCHIP3_UPP_TX_CLKSRC_TXCLK (0x00000001u) + +#define OMAPL_SYSCFG_CFGCHIP3_PLL1_MASTER_LOCK_MASK (0x00000020u) +#define OMAPL_SYSCFG_CFGCHIP3_PLL1_MASTER_LOCK_SHIFT (0x00000005u) +#define OMAPL_SYSCFG_CFGCHIP3_PLL1_MASTER_LOCK_RESETVAL (0x00000000u) +/*----PLL1_MASTER_LOCK Tokens----*/ +#define OMAPL_SYSCFG_CFGCHIP3_PLL1_MASTER_LOCK_FREE (0x00000000u) +#define OMAPL_SYSCFG_CFGCHIP3_PLL1_MASTER_LOCK_LOCK (0x00000001u) + +#define OMAPL_SYSCFG_CFGCHIP3_ASYNC3_CLKSRC_MASK (0x00000010u) +#define OMAPL_SYSCFG_CFGCHIP3_ASYNC3_CLKSRC_SHIFT (0x00000004u) +#define OMAPL_SYSCFG_CFGCHIP3_ASYNC3_CLKSRC_RESETVAL (0x00000000u) +/*----ASYNC3_CLKSRC Tokens----*/ +#define OMAPL_SYSCFG_CFGCHIP3_ASYNC3_CLKSRC_PLL0 (0x00000000u) +#define OMAPL_SYSCFG_CFGCHIP3_ASYNC3_CLKSRC_PLL1 (0x00000001u) + +#define OMAPL_SYSCFG_CFGCHIP3_PRUEVTSEL_MASK (0x00000008u) +#define OMAPL_SYSCFG_CFGCHIP3_PRUEVTSEL_SHIFT (0x00000003u) +#define OMAPL_SYSCFG_CFGCHIP3_PRUEVTSEL_RESETVAL (0x00000000u) +/*----PRUEVTSEL Tokens----*/ +#define OMAPL_SYSCFG_CFGCHIP3_PRUEVTSEL_NORMAL (0x00000000u) +#define OMAPL_SYSCFG_CFGCHIP3_PRUEVTSEL_ALTERNATE (0x00000001u) + +#define OMAPL_SYSCFG_CFGCHIP3_DIV4P5ENA_MASK (0x00000004u) +#define OMAPL_SYSCFG_CFGCHIP3_DIV4P5ENA_SHIFT (0x00000002u) +#define OMAPL_SYSCFG_CFGCHIP3_DIV4P5ENA_RESETVAL (0x00000000u) +/*----DIV4P5ENA Tokens----*/ +#define OMAPL_SYSCFG_CFGCHIP3_DIV4P5ENA_DISABLE (0x00000000u) +#define OMAPL_SYSCFG_CFGCHIP3_DIV4P5ENA_ENABLE (0x00000001u) + +#define OMAPL_SYSCFG_CFGCHIP3_EMA_CLKSRC_MASK (0x00000002u) +#define OMAPL_SYSCFG_CFGCHIP3_EMA_CLKSRC_SHIFT (0x00000001u) +#define OMAPL_SYSCFG_CFGCHIP3_EMA_CLKSRC_RESETVAL (0x00000000u) +/*----EMA_CLKSRC Tokens----*/ +#define OMAPL_SYSCFG_CFGCHIP3_EMA_CLKSRC_PLLCTRL_SYSCLK3 (0x00000000u) +#define OMAPL_SYSCFG_CFGCHIP3_EMA_CLKSRC_4P5_PLL (0x00000001u) + +#define OMAPL_SYSCFG_CFGCHIP3_RESETVAL (0x00000100u) + +#endif diff --git a/drivers/net/can/omapl_pru/pru_can_api.c b/drivers/net/can/omapl_pru/pru_can_api.c new file mode 100644 index 0000000..a554ac2 --- /dev/null +++ b/drivers/net/can/omapl_pru/pru_can_api.c @@ -0,0 +1,1683 @@ +/* + * Copyright (C) 2010 Texas Instruments Incorporated + * Author: Wilfred Felix + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind, + * whether express or implied; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#include <mach/pru/pru.h> +#include "pru_can_api.h" +#include "omapl_syscfg0_OMAPL138.h" + +static can_emulation_drv_inst gstrcanemulationinst[ecanmaxinst]; +static u32 gu32canpruiomapaddress; +static u32 gu32cansyscfgmapaddress; +static u32 gu32canpsc1mapaddress; +static u32 gu32canpsc0mapaddress; +static u32 gu32pruclock; + +/* + * pru_can_enable() Configure and Enable PRU0 and PRU1 of OMAP L138. + * + * This API will be called by the Application to Configure and + * Enable PRU0 and PRU1 + * + * return SUCCESS or FAILURE + */ +s16 pru_can_enable(void) +{ + OMAPL_PrucoreRegsOvly hPru; + OMAPL_SyscfgRegsOvly sysCfg0; + s16 s16returncapture; + + /* Set pru to Alternate mode for timer interrupts */ + sysCfg0 = (OMAPL_SyscfgRegsOvly) gu32cansyscfgmapaddress; + + sysCfg0->KICK0R = 0x83E70B13; + sysCfg0->KICK1R = 0x95A4F1E0; + sysCfg0->CFGCHIP3 |= (OMAPL_SYSCFG_CFGCHIP3_PRUEVTSEL_ALTERNATE << + OMAPL_SYSCFG_CFGCHIP3_PRUEVTSEL_SHIFT); + sysCfg0->KICK0R = 0x0; + sysCfg0->KICK1R = 0x0; + + /* Enable PRU Sub System */ + s16returncapture = pru_can_psc_enable(); + if (s16returncapture == -1) { + return -1; + } + /* Reset PRU 0 */ + hPru = (OMAPL_PrucoreRegsOvly) (gu32canpruiomapaddress | + OMAPL_PRUCANCORE_0_REGS); + hPru->CONTROL = OMAPL_PRUCORE_CONTROL_RESETVAL; + + /* Reset PRU 0 */ + hPru = (OMAPL_PrucoreRegsOvly) (gu32canpruiomapaddress | + OMAPL_PRUCANCORE_1_REGS); + hPru->CONTROL = OMAPL_PRUCORE_CONTROL_RESETVAL; + + return 0; +} +/* + * pru_can_disable() Disable PRU0 and PRU1 of OMAP L138. + * + * This API will be called by the Application to disable PRU0 and PRU1 + * + * return SUCCESS or FAILURE + */ +s16 pru_can_disable(void) +{ + OMAPL_PrucoreRegsOvly hPru; + s16 s16returncapture; + + hPru = (OMAPL_PrucoreRegsOvly) (gu32canpruiomapaddress | + OMAPL_PRUCANCORE_0_REGS); + OMAPL_PRU_FINST(hPru->CONTROL, PRUCORE_CONTROL_COUNTENABLE, DISABLE); + OMAPL_PRU_FINST(hPru->CONTROL, PRUCORE_CONTROL_ENABLE, DISABLE); + hPru->CONTROL = OMAPL_PRUCORE_CONTROL_RESETVAL; + hPru = (OMAPL_PrucoreRegsOvly) (gu32canpruiomapaddress | + OMAPL_PRUCANCORE_1_REGS); + OMAPL_PRU_FINST(hPru->CONTROL, PRUCORE_CONTROL_COUNTENABLE, DISABLE); + OMAPL_PRU_FINST(hPru->CONTROL, PRUCORE_CONTROL_ENABLE, DISABLE); + hPru->CONTROL = OMAPL_PRUCORE_CONTROL_RESETVAL; + s16returncapture = pru_can_psc_disable(); + if (s16returncapture == -1) { + return -1; + } + + return 0; +} + +/* + * pru_can_run () Allows the PRU0 or PRU1 of OMAP + * L138 to execute the code loaded into its Instruction RAM + * + * This API will be called by the Application to execute the + * instruction in PRU + * + * param u8prunum The PRU number to initiate execution + * + * return SUCCESS or FAILURE + */ +s16 pru_can_run(u8 u8prunum) +{ + OMAPL_PrucoreRegsOvly hPru; + + if (u8prunum == OMAPL_PRUCORE_0) { + hPru = (OMAPL_PrucoreRegsOvly) (gu32canpruiomapaddress | + OMAPL_PRUCANCORE_0_REGS); + } else if (u8prunum == OMAPL_PRUCORE_1) { + hPru = (OMAPL_PrucoreRegsOvly) (gu32canpruiomapaddress | + OMAPL_PRUCANCORE_1_REGS); + } else { + return -1; + } + OMAPL_PRU_FINST(hPru->CONTROL, PRUCORE_CONTROL_COUNTENABLE, ENABLE); + OMAPL_PRU_FINST(hPru->CONTROL, PRUCORE_CONTROL_ENABLE, ENABLE); + + return 0; +} + +/* + * pru_can_psc_enable () Enable state transition of PRU + * This API will be called by the Application for state + * transition of PRU + * + * param None + * + * return SUCCESS or FAILURE + */ +s16 pru_can_psc_enable(void) +{ + u32 u32timeout; + bool btransitioncomplete; + OMAPL_PscRegsOvly PSC = (OMAPL_PscRegsOvly) gu32canpsc0mapaddress; + u32timeout = 0; + btransitioncomplete = false; + + while (btransitioncomplete == false) { + if (OMAPL_PRU_FEXT(PSC->PTSTAT, PSC_PTSTAT_GOSTAT0) == + OMAPL_PSC_PTSTAT_GOSTAT0_IN_TRANSITION) { + btransitioncomplete = true; + } + u32timeout++; + if (u32timeout == PRU_CAN_INIT_MAX_TIMEOUT) { + return -1; + } + } + + if (OMAPL_PRU_FEXT(PSC->MDSTAT[OMAPL_PSC_PRU], PSC_MDSTAT_STATE) == + OMAPL_PSC_MDSTAT_STATE_ENABLE) { + return 0; + } + OMAPL_PRU_FINST(PSC->MDCTL[OMAPL_PSC_PRU], PSC_MDCTL_NEXT, ENABLE); + OMAPL_PRU_FINST(PSC->PTCMD, PSC_PTCMD_GO0, SET); + u32timeout = 0; + btransitioncomplete = false; + while (btransitioncomplete == false) { + if (OMAPL_PRU_FEXT(PSC->PTSTAT, PSC_PTSTAT_GOSTAT0) == + OMAPL_PSC_PTSTAT_GOSTAT0_IN_TRANSITION) { + btransitioncomplete = true; + } + u32timeout++; + if (u32timeout == PRU_CAN_INIT_MAX_TIMEOUT) { + return -1; + } + } + + u32timeout = 0; + btransitioncomplete = false; + while (btransitioncomplete == false) { + if (OMAPL_PRU_FEXT(PSC->MDSTAT[OMAPL_PSC_PRU], PSC_MDSTAT_STATE) != + OMAPL_PSC_MDSTAT_STATE_ENABLE) { + btransitioncomplete = true; + } + u32timeout++; + if (u32timeout == PRU_CAN_INIT_MAX_TIMEOUT) { + return -1; + } + } + + return 0; +} + +/* + * pru_can_psc_disable () Disable state transition of PRU + * + * This API will be called by the Application for disabling + * state transition of PRU + * + * return SUCCESS or FAILURE + */ +s16 pru_can_psc_disable(void) +{ + + u32 u32timeout; + bool btransitioncomplete; + OMAPL_PscRegsOvly PSC = (OMAPL_PscRegsOvly) gu32canpsc0mapaddress; + u32timeout = 0; + btransitioncomplete = false; + + while (btransitioncomplete == false) { + if (OMAPL_PRU_FEXT(PSC->PTSTAT, PSC_PTSTAT_GOSTAT0) == + OMAPL_PSC_PTSTAT_GOSTAT0_IN_TRANSITION) { + btransitioncomplete = true; + } + u32timeout++; + if (u32timeout == PRU_CAN_INIT_MAX_TIMEOUT) { + return -1; + } + } + if (OMAPL_PRU_FEXT(PSC->MDSTAT[OMAPL_PSC_PRU], PSC_MDSTAT_STATE) == + OMAPL_PSC_MDSTAT_STATE_SYNCRST) { + return 0; + } + OMAPL_PRU_FINST(PSC->MDCTL[OMAPL_PSC_PRU], PSC_MDCTL_NEXT, SYNCRST); + OMAPL_PRU_FINST(PSC->PTCMD, PSC_PTCMD_GO0, SET); + u32timeout = 0; + btransitioncomplete = false; + while (btransitioncomplete == false) { + if (OMAPL_PRU_FEXT(PSC->PTSTAT, PSC_PTSTAT_GOSTAT0) == + OMAPL_PSC_PTSTAT_GOSTAT0_IN_TRANSITION) { + btransitioncomplete = true; + } + u32timeout++; + if (u32timeout == PRU_CAN_INIT_MAX_TIMEOUT) { + return -1; + } + } + u32timeout = 0; + btransitioncomplete = false; + while (btransitioncomplete == false) { + if (OMAPL_PRU_FEXT(PSC->MDSTAT[OMAPL_PSC_PRU], PSC_MDSTAT_STATE) != + OMAPL_PSC_MDSTAT_STATE_SYNCRST) { + btransitioncomplete = true; + } + /** If the process is timed out return failure *******************/ + u32timeout++; + if (u32timeout == PRU_CAN_INIT_MAX_TIMEOUT) { + return -1; + } + } + + return 0; +} + +/* + * pru_can_ram_write_data() Download the data into data RAM of + * PRU0 or PRU1 of OMAP L138. This API will be called by the + * Application to download the data into data RAM of PRU0 or PRU1 + * + * u32offset Offset of the data RAM where the data + * has to be written + * + * pu32datatowrite Pointer to a buffer that holds the data + * to be written into RAM + * + * u16wordstowrite Number of words to be written into that RAM + * return SUCCESS or FAILURE + */ +s16 pru_can_ram_write_data(u32 u32offset, u32 *pu32datatowrite, + u16 u16wordstowrite) +{ + + u32 *pu32addresstowrite; + u16 u16loop; + + pu32addresstowrite = (u32 *) (u32offset); + + for (u16loop = 0; u16loop < u16wordstowrite; u16loop++) { + *pu32addresstowrite = *pu32datatowrite; + pu32datatowrite++; + pu32addresstowrite++; + } + + return 0; +} + +/* + * pru_can_ram_read_data() Download the data into data RAM + * of PRU0 or PRU1 of OMAP L138. This API will be called by the + * Application to read the data from data RAM of PRU0 or PRU1 + * + * param u32offset Offset of the data RAM where the + * data has to be read + * + * param pu32datatoread Pointer to a buffer that would hold + * the data to be read from the RAM + * + * param u16wordstoread Number of words to be read from RAM + * + * return SUCCESS or FAILURE + */ +s16 pru_can_ram_read_data(u32 u32offset, u32 *pu32datatoread, + u16 u16wordstoread) +{ + + u32 *pu32addresstoread; + u16 u16loop; + + pu32addresstoread = (u32 *) (u32offset); + + for (u16loop = 0; u16loop < u16wordstoread; u16loop++) { + *pu32datatoread = *pu32addresstoread; + pu32datatoread++; + pu32addresstoread++; + } + + return 0; +} + +/* + * pru_can_download_firmware() Download the firmware + * into PRU0 and PRU1 of OMAP L138. This API will be called by the + * Application to download the code into instruction RAM of PRU0 + * and PRU1 + * + * param pstrfirmwaredata Pointer to structure holding + * firmware data + * + * param u8prunum The PRU number to download firmware + * + * return SUCCESS or FAILURE + */ +s16 pru_can_download_firmware(pru_can_firmware_structure *pstrfirmwaredata, + u8 u8prunum) +{ + u32 *pu32pruinstructionram; + u32 u32codesizeinwords; + u32 *pu32prucode; + u32 u32counter; + pu32pruinstructionram = NULL; + u32codesizeinwords = 0; + + if (pstrfirmwaredata == NULL) { + return -1; + } + if (u8prunum == OMAPL_PRUCORE_0) { + pu32pruinstructionram = (u32 *) (gu32canpruiomapaddress | + PRU0_PROG_RAM_START_OFFSET); + pu32prucode = (u32 *) pstrfirmwaredata->ptr_pru0; + u32codesizeinwords = pstrfirmwaredata->u32_pru0_code_size; + } else if (u8prunum == OMAPL_PRUCORE_1) { + pu32pruinstructionram = (u32 *) (gu32canpruiomapaddress | + PRU1_PROG_RAM_START_OFFSET); + pu32prucode = (u32 *) pstrfirmwaredata->ptr_pru1; + u32codesizeinwords = pstrfirmwaredata->u32_pru1_code_size; + } else { + return -1; + } + + /* Copy PRU code to its instruction RAM */ + for (u32counter = 0; u32counter < u32codesizeinwords; u32counter++) { + pu32pruinstructionram[u32counter] = pu32prucode[u32counter]; + } + + return 0; +} + +/* + * pru_can_set_brp() Updates the BRP register of PRU0 + * and PRU1 of OMAP L138. This API will be called by the + * Application to updtae the BRP register of PRU0 and PRU1 + * + * param u16bitrateprescaler The can bus bitrate + * prescaler value be set + * + * return SUCCESS or FAILURE + */ +s16 pru_can_set_brp(u16 u16bitrateprescaler) +{ + + u32 u32offset; + + if (u16bitrateprescaler > 255) { + return -1; + } + + u32offset = (gu32canpruiomapaddress | PRU_CAN_RX_CLOCK_BRP_REGISTER); + pru_can_ram_write_data(u32offset, (u32 *) &u16bitrateprescaler, 1); + + u32offset = (gu32canpruiomapaddress | PRU_CAN_TX_CLOCK_BRP_REGISTER); + pru_can_ram_write_data(u32offset, (u32 *) &u16bitrateprescaler, 1); + + return 0; + +} + +/* + * pru_can_set_bit_timing() Updates the timing register + * of PRU0 and PRU1 of OMAP L138. This API will be called by + * the Application to updtae the timing register of PRU0 and PRU1 + * + * param pstrcanbittiming Pointer to structure holding + * the bit timing values for can bus. + * + * return SUCCESS or FAILURE + */ +s16 pru_can_set_bit_timing(can_bit_timing_consts *pstrcanbittiming) +{ + + u32 u32offset; + u32 u32serregister; + + u32serregister = 0; + + if (pstrcanbittiming == NULL) { + return -1; + } + + if ((pstrcanbittiming->u8syncjumpwidth > PRU_CAN_MAX_SJW) || + (pstrcanbittiming->u8phseg1 > PRU_CAN_MAX_PHSEG1) || + (pstrcanbittiming->u8phseg2 > PRU_CAN_MAX_PHSEG2)) { + return -1; + } + + u32serregister = u32serregister | + ((pstrcanbittiming->u8syncjumpwidth << 7) | + (pstrcanbittiming->u8phseg1 << 3) | + (pstrcanbittiming->u8phseg2)); + + u32offset = (gu32canpruiomapaddress | PRU_CAN_TX_TIMING_REGISTER); + pru_can_ram_write_data(u32offset, (u32 *) &u32serregister, 1); + + u32offset = (gu32canpruiomapaddress | PRU_CAN_RX_TIMING_REGISTER); + pru_can_ram_write_data(u32offset, (u32 *) &u32serregister, 1); + + return 0; +} + + +/* + * pru_can_calculatetiming() Updates the timing values of + * PRU0 and PRU1 of OMAP L138. This API will be called by the + * Application to updtae the timing values of PRU0 and PRU1 + * + * param u32canbittiming Bit timing values for can bus + * + * param u32bitrateprescaler Bit Rate Prescaler for can bus + * + * return SUCCESS or FAILURE + */ +s16 pru_can_calculatetiming(u32 pru_freq, u32 bit_rate) +{ + u16 u16phaseseg1; + u16 u16phaseseg2; + u32 u32offset; + u32 u32TimingValue; + u32 u32SetupValue; + u32TimingValue = TIMER_CLK_FREQ / bit_rate; + u32offset = (gu32canpruiomapaddress | PRU_CAN_TIMING_VAL_TX); + pru_can_ram_write_data(u32offset, (u32 *) &u32TimingValue, 4); + pru_can_ram_read_data(u32offset, (u32 *) &u32TimingValue, 4); + u32SetupValue = + (GPIO_SETUP_DELAY * (pru_freq / 1000000) / 1000) / + DELAY_LOOP_LENGTH; + u32offset = (gu32canpruiomapaddress | (PRU_CAN_TIMING_VAL_TX_SJW)); + pru_can_ram_write_data(u32offset, (u32 *) &u32SetupValue, 4); + u16phaseseg1 = (u16) (u32TimingValue / 2); + u16phaseseg2 = u32TimingValue - u16phaseseg1; + u16phaseseg1 -= TIMER_SETUP_DELAY; + u16phaseseg2 -= TIMER_SETUP_DELAY; + u32SetupValue = (u16phaseseg1 << 16) | u16phaseseg2; + u32offset = (gu32canpruiomapaddress | PRU_CAN_TIMING_VAL_RX); + pru_can_ram_write_data(u32offset, (u32 *) &u32SetupValue, 4); + u32offset = (gu32canpruiomapaddress | (PRU_CAN_TIMING_VAL_RX + 4)); + pru_can_ram_write_data(u32offset, (u32 *) &u32TimingValue, 4); + + return 0; +} + + +/* + * pru_can_write_data_to_mailbox() Updates the transmit + * mailboxes of PRU1 of OMAP L138. This API will be called by + * the Application to updtae the transmit mailboxes of PRU1 + * + * param pu16canframedata Can mailbox data buffer + * + * param u8mailboxnum Mailbox to be updated + * + * return SUCCESS or FAILURE + */ +s16 pru_can_write_data_to_mailbox(can_emulation_app_hndl *pstrcanemuapphndl) +{ + s16 s16subrtnretval; + u32 u32offset; + + if (pstrcanemuapphndl == NULL) { + return -1; + } + + switch ((u8) pstrcanemuapphndl->ecanmailboxnumber) { + case 0: + u32offset = (gu32canpruiomapaddress | PRU_CAN_TX_MAILBOX0); + break; + case 1: + u32offset = (gu32canpruiomapaddress | PRU_CAN_TX_MAILBOX1); + break; + case 2: + u32offset = (gu32canpruiomapaddress | PRU_CAN_TX_MAILBOX2); + break; + case 3: + u32offset = (gu32canpruiomapaddress | PRU_CAN_TX_MAILBOX3); + break; + case 4: + u32offset = (gu32canpruiomapaddress | PRU_CAN_TX_MAILBOX4); + break; + case 5: + u32offset = (gu32canpruiomapaddress | PRU_CAN_TX_MAILBOX5); + break; + case 6: + u32offset = (gu32canpruiomapaddress | PRU_CAN_TX_MAILBOX6); + break; + case 7: + u32offset = (gu32canpruiomapaddress | PRU_CAN_TX_MAILBOX7); + break; + default: + return -1; + } + + s16subrtnretval = pru_can_ram_write_data(u32offset, + (u32 *) &(pstrcanemuapphndl->strcanmailbox), 4); + if (s16subrtnretval == -1) { + return -1; + } + return 0; +} + +/* + * pru_can_get_data_from_mailbox() Receive data from the + * receive mailboxes of PRU0 of OMAP L138. This API will be called by + * the Application to get data from the receive mailboxes of PRU0 + * + * param pu16canframedata Can mailbox data buffer + * + * param u8mailboxnum Mailbox to be updated + * + * return SUCCESS or FAILURE + */ +s16 pru_can_get_data_from_mailbox(can_emulation_app_hndl *pstrcanemuapphndl) +{ + s16 s16subrtnretval; + u32 u32offset; + + if (pstrcanemuapphndl == NULL) { + return -1; + } + + switch ((u8) pstrcanemuapphndl->ecanmailboxnumber) { + case 0: + u32offset = (gu32canpruiomapaddress | PRU_CAN_RX_MAILBOX0); + break; + case 1: + u32offset = (gu32canpruiomapaddress | PRU_CAN_RX_MAILBOX1); + break; + case 2: + u32offset = (gu32canpruiomapaddress | PRU_CAN_RX_MAILBOX2); + break; + case 3: + u32offset = (gu32canpruiomapaddress | PRU_CAN_RX_MAILBOX3); + break; + case 4: + u32offset = (gu32canpruiomapaddress | PRU_CAN_RX_MAILBOX4); + break; + case 5: + u32offset = (gu32canpruiomapaddress | PRU_CAN_RX_MAILBOX5); + break; + case 6: + u32offset = (gu32canpruiomapaddress | PRU_CAN_RX_MAILBOX6); + break; + case 7: + u32offset = (gu32canpruiomapaddress | PRU_CAN_RX_MAILBOX7); + break; + case 8: + u32offset = (gu32canpruiomapaddress | PRU_CAN_RX_MAILBOX8); + break; + default: + return -1; + } + + s16subrtnretval = + pru_can_ram_read_data(u32offset, + (u32 *) &(pstrcanemuapphndl->strcanmailbox), + 4); + if (s16subrtnretval == -1) { + return -1; + } + return 0; +} + +/* + * pru_can_receive_id_map() Receive mailboxes ID Mapping of + * PRU0 of OMAP L138. This API will be called by the Application + * to map the IDs to receive mailboxes of PRU0 + * + * param u32nodeid Can node ID + * + * param ecanmailboxno Mailbox to be mapped + * + * return SUCCESS or FAILURE + */ +s16 pru_can_receive_id_map(u32 u32nodeid, can_mailbox_number ecanmailboxno) +{ + + pru_can_ram_write_data((gu32canpruiomapaddress | (PRU_CAN_ID_MAP + + (((u8) ecanmailboxno) * 4))), (u32 *) &u32nodeid, 1); + + return 0; +} + +/* + * pru_can_get_interrupt_status() Gets the interrupts + * status register value. This API will be called by the Application + * to get the interrupts status register value + * + * param pu32intrstatus Pointer to a var where interrupt + * status register value has to be written + * + * param u8prunumber PRU number for which IntStatusReg + * has to be read + * + * return SUCCESS or FAILURE + */ +s16 pru_can_get_interrupt_status(can_emulation_app_hndl *pstrcanemuapphndl) +{ + u32 u32offset; + s16 s16subrtnretval = -1; + + if (pstrcanemuapphndl == NULL) { + return -1; + } + + if (pstrcanemuapphndl->u8prunumber == OMAPL_PRUCORE_1) { + u32offset = (gu32canpruiomapaddress | + PRU_CAN_TX_INTERRUPT_STATUS_REGISTER); + } else if (pstrcanemuapphndl->u8prunumber == OMAPL_PRUCORE_0) { + u32offset = (gu32canpruiomapaddress | + PRU_CAN_RX_INTERRUPT_STATUS_REGISTER); + } else { + return -1; + } + + s16subrtnretval = pru_can_ram_read_data(u32offset, + (u32 *) &pstrcanemuapphndl->u32interruptstatus, 1); + if (s16subrtnretval == -1) { + return -1; + } + + return 0; +} + +/* + * pru_can_get_global_status() Gets the globalstatus + * register value. This API will be called by the Application + * to get the global status register value + * + * param pu32globalstatus Pointer to a var where global + * status register value has to be written + * + * param u8prunumber PRU number for which GlobalStatusReg + * has to be read + * + * return SUCCESS or FAILURE + */ +s16 pru_can_get_global_status(can_emulation_app_hndl *pstrcanemuapphndl) +{ + u32 u32offset; + int s16subrtnretval = -1; + + if (pstrcanemuapphndl == NULL) { + return -1; + } + + if (pstrcanemuapphndl->u8prunumber == OMAPL_PRUCORE_1) { + u32offset = (gu32canpruiomapaddress | + PRU_CAN_TX_GLOBAL_STATUS_REGISTER); + } else if (pstrcanemuapphndl->u8prunumber == OMAPL_PRUCORE_0) { + u32offset = (gu32canpruiomapaddress | + PRU_CAN_RX_GLOBAL_STATUS_REGISTER); + } else { + return -1; + } + + s16subrtnretval = pru_can_ram_read_data(u32offset, + (u32 *) &pstrcanemuapphndl->u32globalstatus, 1); + if (s16subrtnretval == -1) { + return -1; + } + + return 0; +} + + +/* + * pru_can_get_mailbox_status() Gets the mailbox status + * register value. This API will be called by the Application + * to get the mailbox status register value + * + * param pu32globalstatus Pointer to a var where global + * status register value has to be written + * + * param u8prunumber PRU number for which GlobalStatusReg + * has to be read + * + * return SUCCESS or FAILURE + */ +s16 pru_can_get_mailbox_status(can_emulation_app_hndl *pstrcanemuapphndl) +{ + u32 u32offset; + s16 s16subrtnretval = -1; + + if (pstrcanemuapphndl == NULL) { + return -1; + } + + if (pstrcanemuapphndl->u8prunumber == OMAPL_PRUCORE_1) { + switch (pstrcanemuapphndl->ecanmailboxnumber) { + case 0: + u32offset = + (gu32canpruiomapaddress | + PRU_CAN_TX_MAILBOX0_STATUS_REGISTER); + break; + case 1: + u32offset = + (gu32canpruiomapaddress | + PRU_CAN_TX_MAILBOX1_STATUS_REGISTER); + break; + case 2: + u32offset = + (gu32canpruiomapaddress | + PRU_CAN_TX_MAILBOX2_STATUS_REGISTER); + break; + case 3: + u32offset = + (gu32canpruiomapaddress | + PRU_CAN_TX_MAILBOX3_STATUS_REGISTER); + break; + case 4: + u32offset = + (gu32canpruiomapaddress | + PRU_CAN_TX_MAILBOX4_STATUS_REGISTER); + break; + case 5: + u32offset = + (gu32canpruiomapaddress | + PRU_CAN_TX_MAILBOX5_STATUS_REGISTER); + break; + case 6: + u32offset = + (gu32canpruiomapaddress | + PRU_CAN_TX_MAILBOX6_STATUS_REGISTER); + break; + case 7: + u32offset = + (gu32canpruiomapaddress | + PRU_CAN_TX_MAILBOX7_STATUS_REGISTER); + break; + default: + return -1; + } + } + + else if (pstrcanemuapphndl->u8prunumber == OMAPL_PRUCORE_0) { + switch (pstrcanemuapphndl->ecanmailboxnumber) { + case 0: + u32offset = + (gu32canpruiomapaddress | + PRU_CAN_RX_MAILBOX0_STATUS_REGISTER); + break; + case 1: + u32offset = + (gu32canpruiomapaddress | + PRU_CAN_RX_MAILBOX1_STATUS_REGISTER); + break; + case 2: + u32offset = + (gu32canpruiomapaddress | + PRU_CAN_RX_MAILBOX2_STATUS_REGISTER); + break; + case 3: + u32offset = + (gu32canpruiomapaddress | + PRU_CAN_RX_MAILBOX3_STATUS_REGISTER); + break; + case 4: + u32offset = + (gu32canpruiomapaddress | + PRU_CAN_RX_MAILBOX4_STATUS_REGISTER); + break; + case 5: + u32offset = + (gu32canpruiomapaddress | + PRU_CAN_RX_MAILBOX5_STATUS_REGISTER); + break; + case 6: + u32offset = + (gu32canpruiomapaddress | + PRU_CAN_RX_MAILBOX6_STATUS_REGISTER); + break; + case 7: + u32offset = + (gu32canpruiomapaddress | + PRU_CAN_RX_MAILBOX7_STATUS_REGISTER); + break; + case 8: + u32offset = + (gu32canpruiomapaddress | + PRU_CAN_RX_MAILBOX8_STATUS_REGISTER); + break; + default: + return -1; + } + } + + else { + return -1; + } + + s16subrtnretval = pru_can_ram_read_data(u32offset, + (u32 *) &pstrcanemuapphndl->u32mailboxstatus, 1); + if (s16subrtnretval == -1) { + return -1; + } + + return 0; +} + +s16 pru_can_transfer_mode_set(bool btransfer_flag, + can_transfer_direction ecan_trx) +{ + u32 u32offset; + u32 u32value; + + if (ecan_trx == ecantransmit) { + u32offset = (gu32canpruiomapaddress | PRU_CAN_RX_GLOBAL_STATUS_REGISTER); + pru_can_ram_read_data(u32offset, &u32value, 1); + if (btransfer_flag == true) { + u32value &= 0x1F; + u32value |= 0x80; + } else { + u32value &= 0x7F; + } + pru_can_ram_write_data(u32offset, &u32value, 1); + u32offset = (gu32canpruiomapaddress | PRU_CAN_TX_GLOBAL_STATUS_REGISTER); + pru_can_ram_write_data(u32offset, &u32value, 1); + } else if (ecan_trx == ecanreceive) { + u32offset = (gu32canpruiomapaddress | PRU_CAN_RX_GLOBAL_STATUS_REGISTER); + pru_can_ram_read_data(u32offset, &u32value, 1); + if (btransfer_flag == true) { + u32value &= 0x1F; + u32value |= 0x40; + } else { + u32value &= 0xBF; + } + pru_can_ram_write_data(u32offset, &u32value, 1); + u32offset = (gu32canpruiomapaddress | PRU_CAN_TX_GLOBAL_STATUS_REGISTER); + pru_can_ram_write_data(u32offset, &u32value, 1); + } else + return -1; + + return 0; +} + +/* + * pru_can_configuration_mode_set() Sets the timing value + * for data transfer. This API will be called by the Application + * to set timing valus for data transfer + * + * param bconfigmodeenabledisableflag set the timing parameters + * + * return SUCCESS or FAILURE + */ +s16 pru_can_configuration_mode_set(bool bconfigmodeenabledisableflag) +{ + + u32 u32bitrateprescaler; + u32 u32canbittiming; + + pru_can_ram_read_data((gu32canpruiomapaddress | + PRU_CAN_TX_CLOCK_BRP_REGISTER), (u32 *) &u32bitrateprescaler, 1); + pru_can_ram_read_data((gu32canpruiomapaddress | + PRU_CAN_TX_TIMING_REGISTER), (u32 *) &u32canbittiming, 1); + + if (bconfigmodeenabledisableflag == 1) { + pru_can_calculatetiming(u32canbittiming, u32bitrateprescaler); + } + + else { + pru_can_calculatetiming(0, 0); + } + + return 0; +} + +/* + * pru_can_emulation_init() Initializes the Can + * Emulation Parameters. This API will be called by the Application + * to Initialize the Can Emulation Parameters + * + * param pstr_pru_iomap Pointer to structure holding + * the io map addresses + * + * param u32pruclock PRU Clock value + * + * return SUCCESS or FAILURE + */ +s16 pru_can_emulation_init(arm_pru_iomap *pstr_pru_iomap, u32 u32pruclock) +{ + u32 u32offset; + u32 u32value; + s16 s16subrtnretval = -1; + u8 u8loop; + + for (u8loop = 0; u8loop < (u8) ecanmaxinst; u8loop++) { + gstrcanemulationinst[u8loop].bcaninststate = (bool) 0; + gstrcanemulationinst[u8loop].ecantransferdirection = + (can_transfer_direction) 0; + gstrcanemulationinst[u8loop].u32apphandlerptr = 0; + } + + gu32canpruiomapaddress = (u32) pstr_pru_iomap->pru_io_addr; + gu32canpsc0mapaddress = (u32) pstr_pru_iomap->psc0_io_addr; + gu32canpsc1mapaddress = (u32) pstr_pru_iomap->psc1_io_addr; + gu32cansyscfgmapaddress = (u32) pstr_pru_iomap->syscfg_io_addr; + gu32pruclock = u32pruclock; + + u32offset = gu32canpruiomapaddress | (PRU_CAN_TX_GLOBAL_CONTROL_REGISTER & + 0xFFFF); + u32value = 0x00000000; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_CAN_TX_GLOBAL_STATUS_REGISTER & + 0xFFFF); + u32value = 0x00000040; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + u32offset = gu32canpruiomapaddress | (PRU_CAN_RX_GLOBAL_STATUS_REGISTER & + 0xFFFF); + u32value = 0x00000040; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_CAN_TX_INTERRUPT_MASK_REGISTER & + 0xFFFF); + u32value = 0x00004000; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | + (PRU_CAN_TX_INTERRUPT_STATUS_REGISTER & 0xFFFF); + u32value = 0x00000000; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_CAN_TX_MAILBOX0_STATUS_REGISTER & + 0xFFFF); + u32value = 0x00000001; + s16subrtnretval = + pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_CAN_TX_MAILBOX1_STATUS_REGISTER & + 0xFFFF); + u32value = 0x00000001; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_CAN_TX_MAILBOX2_STATUS_REGISTER & + 0xFFFF); + u32value = 0x00000001; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_CAN_TX_MAILBOX3_STATUS_REGISTER & + 0xFFFF); + u32value = 0x00000001; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_CAN_TX_MAILBOX4_STATUS_REGISTER & + 0xFFFF); + u32value = 0x00000001; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_CAN_TX_MAILBOX5_STATUS_REGISTER & + 0xFFFF); + u32value = 0x00000001; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_CAN_TX_MAILBOX6_STATUS_REGISTER & + 0xFFFF); + u32value = 0x00000001; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_CAN_TX_MAILBOX7_STATUS_REGISTER & + 0xFFFF); + u32value = 0x00000001; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_CAN_TX_ERROR_COUNTER_REGISTER & + 0xFFFF); + u32value = 0x00000000; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_CAN_TX_TIMING_REGISTER & + 0xFFFF); + u32value = 0x00000000; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_CAN_TX_CLOCK_BRP_REGISTER & + 0xFFFF); + u32value = 0x00000000; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_CAN_TX_ERROR_COUNTER_REGISTER & + 0xFFFF); + u32value = 0x00000000; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_INTC_POLARITY0 & 0xFFFF); + u32value = 0xFFFFFFFF; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + u32offset = gu32canpruiomapaddress | (PRU_INTC_POLARITY1 & 0xFFFF); + u32value = 0xFFFFFFFF; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + u32offset = gu32canpruiomapaddress | (PRU_INTC_TYPE0 & 0xFFFF); + u32value = 0x1C000000; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + u32offset = gu32canpruiomapaddress | (PRU_INTC_TYPE1 & 0xFFFF); + u32value = 0x00000000; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_INTC_HSTINTENIDXCLR & 0xFFFF); + u32value = 0x0; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_INTC_GLBLEN & 0xFFFF); + u32value = 0x1; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + /* tx intr map arm->pru */ + u32offset = gu32canpruiomapaddress | (PRU_INTC_HSTINTENIDXSET & 0xFFFF); + u32value = 0x0; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_INTC_HOSTMAP0 & 0xFFFF); + u32value = 0x03020100; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_INTC_HOSTMAP1 & 0xFFFF); + u32value = 0x07060504; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_INTC_HOSTMAP2 & 0xFFFF); + u32value = 0x0000908; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_INTC_CHANMAP0 & 0xFFFF); + u32value = 0; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_INTC_CHANMAP8 & 0xFFFF); + u32value = 0x00020200; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_INTC_STATIDXCLR & 0xFFFF); + u32value = 32; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } +#if 1 + u32offset = gu32canpruiomapaddress | (PRU_INTC_STATIDXCLR & 0xFFFF); + u32value = 19; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_INTC_ENIDXSET & 0xFFFF); + u32value = 19; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + u32offset = gu32canpruiomapaddress | (PRU_INTC_STATIDXCLR & 0xFFFF); + u32value = 18; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_INTC_ENIDXSET & 0xFFFF); + u32value = 18; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_INTC_STATIDXCLR & 0xFFFF); + u32value = 34; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_INTC_ENIDXSET & 0xFFFF); + u32value = 34; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } +#endif + + u32offset = gu32canpruiomapaddress | (PRU_INTC_ENIDXSET & 0xFFFF); + u32value = 32; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_INTC_HOSTINTEN & 0xFFFF); + u32value = 0x5; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + +/* PRU0 - Rx Internal Registers Initializations */ + + u32offset = gu32canpruiomapaddress | (PRU_CAN_RX_GLOBAL_CONTROL_REGISTER & + 0xFFFF); + u32value = 0x00000000; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_CAN_RX_GLOBAL_STATUS_REGISTER & + 0xFFFF); + u32value = 0x00000040; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_CAN_RX_INTERRUPT_MASK_REGISTER & + 0xFFFF); + u32value = 0x00004000; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | + (PRU_CAN_RX_INTERRUPT_STATUS_REGISTER & 0xFFFF); + u32value = 0x00000000; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_CAN_RX_MAILBOX0_STATUS_REGISTER & + 0xFFFF); + u32value = 0x00000000; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_CAN_RX_MAILBOX1_STATUS_REGISTER & + 0xFFFF); + u32value = 0x0000000; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_CAN_RX_MAILBOX2_STATUS_REGISTER & + 0xFFFF); + u32value = 0x00000000; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_CAN_RX_MAILBOX3_STATUS_REGISTER & + 0xFFFF); + u32value = 0x00000000; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_CAN_RX_MAILBOX4_STATUS_REGISTER & + 0xFFFF); + u32value = 0x00000000; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_CAN_RX_MAILBOX5_STATUS_REGISTER & + 0xFFFF); + u32value = 0x00000000; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_CAN_RX_MAILBOX6_STATUS_REGISTER & + 0xFFFF); + u32value = 0x00000000; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_CAN_RX_MAILBOX7_STATUS_REGISTER & + 0xFFFF); + u32value = 0x00000000; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_CAN_RX_ERROR_COUNTER_REGISTER & + 0xFFFF); + u32value = 0x00000000; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_CAN_RX_TIMING_REGISTER & 0xFFFF); + u32value = 0x0000000; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + u32offset = gu32canpruiomapaddress | (PRU_CAN_RX_CLOCK_BRP_REGISTER & 0xFFFF); + u32value = 0x00000000; + s16subrtnretval = pru_can_ram_write_data(u32offset, (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + return 0; +} + + +/* + * pru_can_emulation_open() Opens the can emulation for + * application to use. This API will be called by the Application + * to Open the can emulation for application to use. + * + * param pstrcanemuapphndl Pointer to application handler + * structure + * + * return SUCCESS or FAILURE + */ +s16 pru_can_emulation_open(can_emulation_app_hndl *pstrcanemuapphndl) +{ + + if (pstrcanemuapphndl == NULL) { + return -1; + } + + if (gstrcanemulationinst[pstrcanemuapphndl->ecaninstance].bcaninststate + == 1) { + return -1; + } + + gstrcanemulationinst[(u8) pstrcanemuapphndl->ecaninstance].bcaninststate + = (bool) 1; + gstrcanemulationinst[(u8) pstrcanemuapphndl-> + ecaninstance].ecantransferdirection = (can_transfer_direction)(u8) + pstrcanemuapphndl->ecantransferdirection; + gstrcanemulationinst[(u8) pstrcanemuapphndl->ecaninstance]. + u32apphandlerptr = (u32) pstrcanemuapphndl; + + return 0; +} + + +/* + * brief pru_can_emulation_close() Closes the can emulation for other + * applications to use. This API will be called by the Application to Close + * the can emulation for other applications to use + * + * param pstrcanemuapphndl Pointer to application handler structure + * + * return SUCCESS or FAILURE + */ +s16 pru_can_emulation_close(can_emulation_app_hndl *pstrcanemuapphndl) +{ + + if (pstrcanemuapphndl == NULL) { + return -1; + } + if (gstrcanemulationinst[pstrcanemuapphndl->ecaninstance].bcaninststate + == 0) { + return -1; + } + if ((u32) pstrcanemuapphndl != gstrcanemulationinst[(u8) pstrcanemuapphndl-> + ecaninstance].u32apphandlerptr){ + return -1; + } + gstrcanemulationinst[(u8) pstrcanemuapphndl->ecaninstance].bcaninststate + = (bool) 0; + gstrcanemulationinst[(u8) pstrcanemuapphndl-> + ecaninstance].ecantransferdirection = (can_transfer_direction) 0; + gstrcanemulationinst[(u8) pstrcanemuapphndl-> + ecaninstance].u32apphandlerptr = 0; + + return 0; +} + +/* + * brief pru_can_emulation_exit() Diables all the PRUs + * This API will be called by the Application to disable all PRUs + * param None + * return SUCCESS or FAILURE + */ +s16 pru_can_emulation_exit(void) +{ + s16 s16subrtnretval; + + s16subrtnretval = pru_can_disable(); + if (s16subrtnretval == -1) { + return -1; + } + + return 0; +} +s16 pru_can_emulation_sreset(void) +{ + return 0; +} + +s16 pru_can_transfer(u8 u8mailboxnumber, u8 u8prunumber) +{ + u32 u32offset = 0; + u32 u32value = 0; + s16 s16subrtnretval = -1; + + if (OMAPL_PRUCORE_1 == u8prunumber) { + switch (u8mailboxnumber) { + case 0: + u32offset = gu32canpruiomapaddress | + (PRU_CAN_TX_MAILBOX0_STATUS_REGISTER & 0xFFFF); + u32value = 0x00000080; + s16subrtnretval = pru_can_ram_write_data(u32offset, + (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + break; + case 1: + u32offset = gu32canpruiomapaddress | + (PRU_CAN_TX_MAILBOX1_STATUS_REGISTER & 0xFFFF); + u32value = 0x00000080; + s16subrtnretval = pru_can_ram_write_data(u32offset, + (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + break; + case 2: + u32offset = gu32canpruiomapaddress | + (PRU_CAN_TX_MAILBOX2_STATUS_REGISTER & 0xFFFF); + u32value = 0x00000080; + s16subrtnretval = pru_can_ram_write_data(u32offset, + (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + break; + case 3: + u32offset = gu32canpruiomapaddress | + (PRU_CAN_TX_MAILBOX3_STATUS_REGISTER & 0xFFFF); + u32value = 0x00000080; + s16subrtnretval = pru_can_ram_write_data(u32offset, + (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + break; + case 4: + u32offset = gu32canpruiomapaddress | + (PRU_CAN_TX_MAILBOX4_STATUS_REGISTER & 0xFFFF); + u32value = 0x00000080; + s16subrtnretval = pru_can_ram_write_data(u32offset, + (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + break; + case 5: + u32offset = gu32canpruiomapaddress | + (PRU_CAN_TX_MAILBOX5_STATUS_REGISTER & 0xFFFF); + u32value = 0x00000080; + s16subrtnretval = pru_can_ram_write_data(u32offset, + (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + break; + case 6: + u32offset = gu32canpruiomapaddress | + (PRU_CAN_TX_MAILBOX6_STATUS_REGISTER & 0xFFFF); + u32value = 0x00000080; + s16subrtnretval = pru_can_ram_write_data(u32offset, + (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + break; + case 7: + u32offset = gu32canpruiomapaddress | + (PRU_CAN_TX_MAILBOX7_STATUS_REGISTER & 0xFFFF); + u32value = 0x00000080; + s16subrtnretval = pru_can_ram_write_data(u32offset, + (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + break; + default: + return -1; + } + } else { + + u32offset = gu32canpruiomapaddress | + (PRU_CAN_RX_INTERRUPT_STATUS_REGISTER & 0xFFFF); + u32value = 0x00000000; + s16subrtnretval = pru_can_ram_read_data(u32offset, + (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + u32value = u32value & ~(1 << u8mailboxnumber); + s16subrtnretval = pru_can_ram_write_data(u32offset, + (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + + switch (u8mailboxnumber) { + case 0: + u32offset = gu32canpruiomapaddress | + (PRU_CAN_RX_MAILBOX0_STATUS_REGISTER & 0xFFFF); + u32value = 0x00000000; + s16subrtnretval = pru_can_ram_write_data(u32offset, + (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + break; + case 1: + u32offset = gu32canpruiomapaddress | + (PRU_CAN_RX_MAILBOX1_STATUS_REGISTER & 0xFFFF); + u32value = 0x00000000; + s16subrtnretval = pru_can_ram_write_data(u32offset, + (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + break; + case 2: + u32offset = gu32canpruiomapaddress | + (PRU_CAN_RX_MAILBOX2_STATUS_REGISTER & 0xFFFF); + u32value = 0x00000000; + s16subrtnretval = pru_can_ram_write_data(u32offset, + (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + break; + case 3: + u32offset = gu32canpruiomapaddress | + (PRU_CAN_RX_MAILBOX3_STATUS_REGISTER & 0xFFFF); + u32value = 0x00000000; + s16subrtnretval = pru_can_ram_write_data(u32offset, + (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + break; + case 4: + u32offset = gu32canpruiomapaddress | + (PRU_CAN_RX_MAILBOX4_STATUS_REGISTER & 0xFFFF); + u32value = 0x00000000; + s16subrtnretval = pru_can_ram_write_data(u32offset, + (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + break; + case 5: + u32offset = gu32canpruiomapaddress | + (PRU_CAN_RX_MAILBOX5_STATUS_REGISTER & 0xFFFF); + u32value = 0x00000000; + s16subrtnretval = pru_can_ram_write_data(u32offset, + (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + break; + case 6: + u32offset = gu32canpruiomapaddress | + (PRU_CAN_RX_MAILBOX6_STATUS_REGISTER & 0xFFFF); + u32value = 0x00000000; + s16subrtnretval = pru_can_ram_write_data(u32offset, + (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + break; + case 7: + u32offset = gu32canpruiomapaddress | + (PRU_CAN_RX_MAILBOX7_STATUS_REGISTER & 0xFFFF); + u32value = 0x00000000; + s16subrtnretval = pru_can_ram_write_data(u32offset, + (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + break; + default: + return -1; + } + } + return 0; +} + +s16 pru_can_start_or_abort_transmission(bool bcantransmitabortflag) +{ + u32 u32offset; + u32 u32value; + s16 s16subrtnretval; + u32offset = gu32canpruiomapaddress | (PRU_INTC_STATIDXCLR & 0xFFFF); + u32value = 32; + s16subrtnretval = pru_can_ram_write_data(u32offset, + (u32 *) &u32value, 1); + + u32offset = gu32canpruiomapaddress | (PRU_INTC_ENIDXSET & 0xFFFF); + u32value = 32; + s16subrtnretval = pru_can_ram_write_data(u32offset, + (u32 *) &u32value, 1); + + u32offset = gu32canpruiomapaddress | (PRU_INTC_STATIDXSET & 0xFFFF); + u32value = 32; + s16subrtnretval = pru_can_ram_write_data(u32offset, + (u32 *) &u32value, 1); + if (s16subrtnretval == -1) { + return -1; + } + return 0; +} + +s16 pru_can_check_init_status(void) +{ + return 0; +} + +s16 pru_can_mask_ints(u32 int_mask) +{ + return 0; +} + +int pru_can_get_error_cnt(u8 u8prunumber) +{ + return 0; +} + +int pru_can_intc_status_get(void) +{ + u32 u32offset = 0; + u32 u32getvalue = 0; + u32 u32clrvalue = 0; + + u32offset = gu32canpruiomapaddress | (PRU_INTC_STATCLRINT1 & 0xFFFF); + pru_ram_read_data_4byte(u32offset, (u32 *) &u32getvalue, 1); + + if (u32getvalue & 4) + u32clrvalue = 34; /* CLR Event 34 */ + + if (u32getvalue & 2) + u32clrvalue = 33; /* CLR Event 33 */ + + if (u32clrvalue) { + u32offset = gu32canpruiomapaddress | (PRU_INTC_STATIDXCLR & 0xFFFF); + pru_ram_write_data_4byte(u32offset, &u32clrvalue, 1); + } else + return -1; + + return u32getvalue; +} diff --git a/drivers/net/can/omapl_pru/pru_can_api.h b/drivers/net/can/omapl_pru/pru_can_api.h new file mode 100644 index 0000000..5e4b6e7 --- /dev/null +++ b/drivers/net/can/omapl_pru/pru_can_api.h @@ -0,0 +1,1455 @@ +/* + * Copyright (C) 2010 Texas Instruments Incorporated + * Author: Ganeshan N + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind, + * whether express or implied; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#ifndef _PRU_CAN_API_H_ +#define _PRU_CAN_API_H_ + +#include <linux/types.h> +#include <mach/pru/pru.h> + + +#define CAN_BIT_TIMINGS (0x273) + +/* Timer Clock is sourced from DDR freq (PLL1 SYS CLK 2) */ +#define TIMER_CLK_FREQ 132000000 + +#define TIMER_SETUP_DELAY 14 +#define GPIO_SETUP_DELAY 150 + +/* Number of Instruction in the Delay loop */ +#define DELAY_LOOP_LENGTH 2 + +#define PRU1_BASE_ADDR 0x2000 + +#define PRU_CAN_TX_GLOBAL_CONTROL_REGISTER (PRU1_BASE_ADDR) +#define PRU_CAN_TX_GLOBAL_STATUS_REGISTER (PRU1_BASE_ADDR + 0x04) +#define PRU_CAN_TX_INTERRUPT_MASK_REGISTER (PRU1_BASE_ADDR + 0x08) +#define PRU_CAN_TX_INTERRUPT_STATUS_REGISTER (PRU1_BASE_ADDR + 0x0C) +#define PRU_CAN_TX_MAILBOX0_STATUS_REGISTER (PRU1_BASE_ADDR + 0x10) +#define PRU_CAN_TX_MAILBOX1_STATUS_REGISTER (PRU1_BASE_ADDR + 0x14) +#define PRU_CAN_TX_MAILBOX2_STATUS_REGISTER (PRU1_BASE_ADDR + 0x18) +#define PRU_CAN_TX_MAILBOX3_STATUS_REGISTER (PRU1_BASE_ADDR + 0x1C) +#define PRU_CAN_TX_MAILBOX4_STATUS_REGISTER (PRU1_BASE_ADDR + 0x20) +#define PRU_CAN_TX_MAILBOX5_STATUS_REGISTER (PRU1_BASE_ADDR + 0x24) +#define PRU_CAN_TX_MAILBOX6_STATUS_REGISTER (PRU1_BASE_ADDR + 0x28) +#define PRU_CAN_TX_MAILBOX7_STATUS_REGISTER (PRU1_BASE_ADDR + 0x2C) +#define PRU_CAN_TX_ERROR_COUNTER_REGISTER (PRU1_BASE_ADDR + 0x30) +#define PRU_CAN_TX_TIMING_REGISTER (PRU1_BASE_ADDR + 0x34) +#define PRU_CAN_TX_CLOCK_BRP_REGISTER (PRU1_BASE_ADDR + 0x38) + +#define PRU_CAN_TX_MAILBOX0 (PRU1_BASE_ADDR + 0x40) +#define PRU_CAN_TX_MAILBOX1 (PRU1_BASE_ADDR + 0x50) +#define PRU_CAN_TX_MAILBOX2 (PRU1_BASE_ADDR + 0x60) +#define PRU_CAN_TX_MAILBOX3 (PRU1_BASE_ADDR + 0x70) +#define PRU_CAN_TX_MAILBOX4 (PRU1_BASE_ADDR + 0x80) +#define PRU_CAN_TX_MAILBOX5 (PRU1_BASE_ADDR + 0x90) +#define PRU_CAN_TX_MAILBOX6 (PRU1_BASE_ADDR + 0xA0) +#define PRU_CAN_TX_MAILBOX7 (PRU1_BASE_ADDR + 0xB0) + +#define PRU_CAN_TIMING_VAL_TX (PRU1_BASE_ADDR + 0xC0) +#define PRU_CAN_TIMING_VAL_TX_SJW (PRU1_BASE_ADDR + 0xC4) +#define PRU_CAN_TRANSMIT_FRAME (PRU1_BASE_ADDR + 0xE0) + +#define PRU0_BASE_ADDR 0 + +#define PRU_CAN_RX_GLOBAL_CONTROL_REGISTER (PRU0_BASE_ADDR) +#define PRU_CAN_RX_GLOBAL_STATUS_REGISTER (PRU0_BASE_ADDR + 0x04) +#define PRU_CAN_RX_INTERRUPT_MASK_REGISTER (PRU0_BASE_ADDR + 0x08) +#define PRU_CAN_RX_INTERRUPT_STATUS_REGISTER (PRU0_BASE_ADDR + 0x0C) +#define PRU_CAN_RX_MAILBOX0_STATUS_REGISTER (PRU0_BASE_ADDR + 0x10) +#define PRU_CAN_RX_MAILBOX1_STATUS_REGISTER (PRU0_BASE_ADDR + 0x14) +#define PRU_CAN_RX_MAILBOX2_STATUS_REGISTER (PRU0_BASE_ADDR + 0x18) +#define PRU_CAN_RX_MAILBOX3_STATUS_REGISTER (PRU0_BASE_ADDR + 0x1C) +#define PRU_CAN_RX_MAILBOX4_STATUS_REGISTER (PRU0_BASE_ADDR + 0x20) +#define PRU_CAN_RX_MAILBOX5_STATUS_REGISTER (PRU0_BASE_ADDR + 0x24) +#define PRU_CAN_RX_MAILBOX6_STATUS_REGISTER (PRU0_BASE_ADDR + 0x28) +#define PRU_CAN_RX_MAILBOX7_STATUS_REGISTER (PRU0_BASE_ADDR + 0x2C) +#define PRU_CAN_RX_MAILBOX8_STATUS_REGISTER (PRU0_BASE_ADDR + 0x30) +#define PRU_CAN_RX_ERROR_COUNTER_REGISTER (PRU0_BASE_ADDR + 0x34) +#define PRU_CAN_RX_TIMING_REGISTER (PRU0_BASE_ADDR + 0x38) +#define PRU_CAN_RX_CLOCK_BRP_REGISTER (PRU0_BASE_ADDR + 0x3C) + +#define PRU_CAN_RX_MAILBOX0 (PRU0_BASE_ADDR + 0x40) +#define PRU_CAN_RX_MAILBOX1 (PRU0_BASE_ADDR + 0x50) +#define PRU_CAN_RX_MAILBOX2 (PRU0_BASE_ADDR + 0x60) +#define PRU_CAN_RX_MAILBOX3 (PRU0_BASE_ADDR + 0x70) +#define PRU_CAN_RX_MAILBOX4 (PRU0_BASE_ADDR + 0x80) +#define PRU_CAN_RX_MAILBOX5 (PRU0_BASE_ADDR + 0x90) +#define PRU_CAN_RX_MAILBOX6 (PRU0_BASE_ADDR + 0xA0) +#define PRU_CAN_RX_MAILBOX7 (PRU0_BASE_ADDR + 0xB0) +#define PRU_CAN_RX_MAILBOX8 (PRU0_BASE_ADDR + 0xC0) + +#define PRU_CAN_TIMING_VAL_RX (PRU0_BASE_ADDR + 0xD0) +#define PRU_CAN_RECEIVE_FRAME (PRU0_BASE_ADDR + 0xD4) +#define PRU_CAN_ID_MAP (PRU0_BASE_ADDR + 0xF0) + +#define PRU_CAN_ERROR_ACTIVE 128 + +#define CAN_ACK_FAILED 0xE +#define CAN_ARBTR_FAIL 0xD +#define CAN_BIT_ERROR 0xC +#define CAN_TRANSMISSION_SUCCESS 0xA + +#define STD_DATA_FRAME 0x1 +#define EXTD_DATA_FRAME 0x2 +#define STD_REMOTE_FRAME 0x3 +#define EXTD_REMOTE_FRAME 0x4 + +#define PRU_CAN_MAX_SJW 8 +#define PRU_CAN_MAX_PHSEG1 25 +#define PRU_CAN_MAX_PHSEG2 25 + +#define OMAPL_PRUCANCORE_0_REGS 0x7000 +#define OMAPL_PRUCANCORE_1_REGS 0x7800 +#define PRU0_PROG_RAM_START_OFFSET 0x8000 +#define PRU1_PROG_RAM_START_OFFSET 0xC000 +#define PRU_CAN_INIT_MAX_TIMEOUT 0xFF + +typedef enum { + OMAPL_PSC_CC0 = 0, + OMAPL_PSC_TC0 = 1, + OMAPL_PSC_TC1 = 2, + OMAPL_PSC_EMIFA = 3, + OMAPL_PSC_SPI0 = 4, + OMAPL_PSC_MMCSD0 = 5, + OMAPL_PSC_AINTC = 6, + OMAPL_PSC_ARM_RAMROM = 7, + OMAPL_PSC_UART0 = 9, + OMAPL_PSC_SCR0_SS = 10, + OMAPL_PSC_SCR1_SS = 11, + OMAPL_PSC_SCR2_SS = 12, + OMAPL_PSC_PRU = 13, + OMAPL_PSC_ARM = 14, + OMAPL_PSC_DSP = 15 +} OMAPL_Psc0Peripheral; + +typedef enum { + OMAPL_PSC_CC1 = 0, + OMAPL_PSC_USB0 = 1, + OMAPL_PSC_USB1 = 2, + OMAPL_PSC_GPIO = 3, + OMAPL_PSC_UHPI = 4, + OMAPL_PSC_EMAC = 5, + OMAPL_PSC_DDR2_MDDR = 6, + OMAPL_PSC_MCASP0 = 7, + OMAPL_PSC_SATA = 8, + OMAPL_PSC_VPIF = 9, + OMAPL_PSC_SPI1 = 10, + OMAPL_PSC_I2C1 = 11, + OMAPL_PSC_UART1 = 12, + OMAPL_PSC_UART2 = 13, + OMAPL_PSC_MCBSP0 = 14, + OMAPL_PSC_MCBSP1 = 15, + OMAPL_PSC_LCDC = 16, + OMAPL_PSC_EHRPWM = 17, + OMAPL_PSC_MMCSD1 = 18, + OMAPL_PSC_UPP = 19, + OMAPL_PSC_ECAP0_1_2 = 20, + OMAPL_PSC_TC2 = 21, + OMAPL_PSC_SCRF0_SS = 24, + OMAPL_PSC_SCRF1_SS = 25, + OMAPL_PSC_SCRF2_SS = 26, + OMAPL_PSC_SCRF6_SS = 27, + OMAPL_PSC_SCRF7_SS = 28, + OMAPL_PSC_SCRF8_SS = 29, + OMAPL_PSC_BR_F7 = 30, + OMAPL_PSC_SHRAM = 31 +} OMAPL_Psc1Peripheral; + +typedef enum { + ecaninst0 = 0, + ecaninst1, + ecanmaxinst +} can_instance_enum; + +typedef enum { + ecanmailbox0 = 0, + ecanmailbox1, + ecanmailbox2, + ecanmailbox3, + ecanmailbox4, + ecanmailbox5, + ecanmailbox6, + ecanmailbox7 +} can_mailbox_number; + +typedef enum { + ecandirectioninit = 0, + ecantransmit, + ecanreceive +} can_transfer_direction; + +typedef struct { + u16 u16extendedidentifier; + u16 u16baseidentifier; + u8 u8data7; + u8 u8data6; + u8 u8data5; + u8 u8data4; + u8 u8data3; + u8 u8data2; + u8 u8data1; + u8 u8data0; + u16 u16datalength; + u16 u16crc; +} can_mail_box_structure; + +typedef struct { + can_transfer_direction ecantransferdirection; +} can_mailbox_config; + +typedef struct { + can_instance_enum ecaninstance; + can_transfer_direction ecantransferdirection; + can_mail_box_structure strcanmailbox; + can_mailbox_number ecanmailboxnumber; + u8 u8prunumber; + u32 u32globalstatus; + u32 u32interruptstatus; + u32 u32mailboxstatus; +} can_emulation_app_hndl; + +typedef struct { + bool bcaninststate; + can_transfer_direction ecantransferdirection; + u32 u32apphandlerptr; +} can_emulation_drv_inst; + +typedef struct { + u8 u8syncjumpwidth; + u8 u8phseg1; + u8 u8phseg2; +} can_bit_timing_consts; + +typedef struct { + u32 *ptr_pru0; + u32 *ptr_pru1; + u32 u32_pru0_code_size; + u32 u32_pru1_code_size; +} pru_can_firmware_structure; + +/* Field Definition Macros */ + +/* CONTROL */ + +#define OMAPL_PRUCORE_CONTROL_PCRESETVAL_MASK (0xFFFF0000u) +#define OMAPL_PRUCORE_CONTROL_PCRESETVAL_SHIFT (0x00000010u) +#define OMAPL_PRUCORE_CONTROL_PCRESETVAL_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_CONTROL_RUNSTATE_MASK (0x00008000u) +#define OMAPL_PRUCORE_CONTROL_RUNSTATE_SHIFT (0x0000000Fu) +#define OMAPL_PRUCORE_CONTROL_RUNSTATE_RESETVAL (0x00000000u) +/*----RUNSTATE Tokens----*/ +#define OMAPL_PRUCORE_CONTROL_RUNSTATE_HALT (0x00000000u) +#define OMAPL_PRUCORE_CONTROL_RUNSTATE_RUN (0x00000001u) + +#define OMAPL_PRUCORE_CONTROL_SINGLESTEP_MASK (0x00000100u) +#define OMAPL_PRUCORE_CONTROL_SINGLESTEP_SHIFT (0x00000008u) +#define OMAPL_PRUCORE_CONTROL_SINGLESTEP_RESETVAL (0x00000000u) +/*----SINGLESTEP Tokens----*/ +#define OMAPL_PRUCORE_CONTROL_SINGLESTEP_FREERUN (0x00000000u) +#define OMAPL_PRUCORE_CONTROL_SINGLESTEP_SINGLE (0x00000001u) + +#define OMAPL_PRUCORE_CONTROL_COUNTENABLE_MASK (0x00000008u) +#define OMAPL_PRUCORE_CONTROL_COUNTENABLE_SHIFT (0x00000003u) +#define OMAPL_PRUCORE_CONTROL_COUNTENABLE_RESETVAL (0x00000000u) +/*----COUNTENABLE Tokens----*/ +#define OMAPL_PRUCORE_CONTROL_COUNTENABLE_DISABLE (0x00000000u) +#define OMAPL_PRUCORE_CONTROL_COUNTENABLE_ENABLE (0x00000001u) + +#define OMAPL_PRUCORE_CONTROL_SLEEPING_MASK (0x00000004u) +#define OMAPL_PRUCORE_CONTROL_SLEEPING_SHIFT (0x00000002u) +#define OMAPL_PRUCORE_CONTROL_SLEEPING_RESETVAL (0x00000000u) +/*----SLEEPING Tokens----*/ +#define OMAPL_PRUCORE_CONTROL_SLEEPING_NOTASLEEP (0x00000000u) +#define OMAPL_PRUCORE_CONTROL_SLEEPING_ASLEEP (0x00000001u) + +#define OMAPL_PRUCORE_CONTROL_ENABLE_MASK (0x00000002u) +#define OMAPL_PRUCORE_CONTROL_ENABLE_SHIFT (0x00000001u) +#define OMAPL_PRUCORE_CONTROL_ENABLE_RESETVAL (0x00000000u) +/*----ENABLE Tokens----*/ +#define OMAPL_PRUCORE_CONTROL_ENABLE_DISABLE (0x00000000u) +#define OMAPL_PRUCORE_CONTROL_ENABLE_ENABLE (0x00000001u) + +#define OMAPL_PRUCORE_CONTROL_SOFTRESET_MASK (0x00000001u) +#define OMAPL_PRUCORE_CONTROL_SOFTRESET_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_CONTROL_SOFTRESET_RESETVAL (0x00000000u) +/*----SOFTRESET Tokens----*/ +#define OMAPL_PRUCORE_CONTROL_SOFTRESET_RESET (0x00000000u) +#define OMAPL_PRUCORE_CONTROL_SOFTRESET_OUT_OF_RESET (0x00000001u) + +#define OMAPL_PRUCORE_CONTROL_RESETVAL (0x00000000u) + +/* STATUS */ + +#define OMAPL_PRUCORE_STATUS_PCOUNTER_MASK (0x0000FFFFu) +#define OMAPL_PRUCORE_STATUS_PCOUNTER_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_STATUS_PCOUNTER_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_STATUS_RESETVAL (0x00000000u) + +/* WAKEUP */ + +#define OMAPL_PRUCORE_WAKEUP_BITWISEENABLES_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_WAKEUP_BITWISEENABLES_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_WAKEUP_BITWISEENABLES_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_WAKEUP_RESETVAL (0x00000000u) + +/* CYCLECNT */ + +#define OMAPL_PRUCORE_CYCLECNT_CYCLECOUNT_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_CYCLECNT_CYCLECOUNT_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_CYCLECNT_CYCLECOUNT_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_CYCLECNT_RESETVAL (0x00000000u) + +/* STALLCNT */ + +#define OMAPL_PRUCORE_STALLCNT_STALLCOUNT_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_STALLCNT_STALLCOUNT_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_STALLCNT_STALLCOUNT_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_STALLCNT_RESETVAL (0x00000000u) + +/* CONTABBLKIDX0 */ + +#define OMAPL_PRUCORE_CONTABBLKIDX0_C25_MASK (0x000F0000u) +#define OMAPL_PRUCORE_CONTABBLKIDX0_C25_SHIFT (0x00000010u) +#define OMAPL_PRUCORE_CONTABBLKIDX0_C25_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_CONTABBLKIDX0_C24_MASK (0x0000000Fu) +#define OMAPL_PRUCORE_CONTABBLKIDX0_C24_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_CONTABBLKIDX0_C24_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_CONTABBLKIDX0_RESETVAL (0x00000000u) + +/* CONTABBLKIDX1 */ + +#define OMAPL_PRUCORE_CONTABBLKIDX1_C27_MASK (0x000F0000u) +#define OMAPL_PRUCORE_CONTABBLKIDX1_C27_SHIFT (0x00000010u) +#define OMAPL_PRUCORE_CONTABBLKIDX1_C27_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_CONTABBLKIDX1_C26_MASK (0x0000000Fu) +#define OMAPL_PRUCORE_CONTABBLKIDX1_C26_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_CONTABBLKIDX1_C26_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_CONTABBLKIDX1_RESETVAL (0x00000000u) + +/* CONTABPROPTR0 */ + +#define OMAPL_PRUCORE_CONTABPROPTR0_C29_MASK (0xFFFF0000u) +#define OMAPL_PRUCORE_CONTABPROPTR0_C29_SHIFT (0x00000010u) +#define OMAPL_PRUCORE_CONTABPROPTR0_C29_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_CONTABPROPTR0_C28_MASK (0x0000FFFFu) +#define OMAPL_PRUCORE_CONTABPROPTR0_C28_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_CONTABPROPTR0_C28_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_CONTABPROPTR0_RESETVAL (0x00000000u) + +/* CONTABPROPTR1 */ + +#define OMAPL_PRUCORE_CONTABPROPTR1_C31_MASK (0xFFFF0000u) +#define OMAPL_PRUCORE_CONTABPROPTR1_C31_SHIFT (0x00000010u) +#define OMAPL_PRUCORE_CONTABPROPTR1_C31_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_CONTABPROPTR1_C30_MASK (0x0000FFFFu) +#define OMAPL_PRUCORE_CONTABPROPTR1_C30_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_CONTABPROPTR1_C30_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_CONTABPROPTR1_RESETVAL (0x00000000u) + +/* INTGPR0 */ + +#define OMAPL_PRUCORE_INTGPR0_REG_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTGPR0_REG_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTGPR0_REG_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTGPR0_RESETVAL (0x00000000u) + +/* INTGPR1 */ + +#define OMAPL_PRUCORE_INTGPR1_REG_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTGPR1_REG_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTGPR1_REG_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTGPR1_RESETVAL (0x00000000u) + +/* INTGPR2 */ + +#define OMAPL_PRUCORE_INTGPR2_REG_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTGPR2_REG_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTGPR2_REG_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTGPR2_RESETVAL (0x00000000u) + +/* INTGPR3 */ + +#define OMAPL_PRUCORE_INTGPR3_REG_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTGPR3_REG_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTGPR3_REG_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTGPR3_RESETVAL (0x00000000u) + +/* INTGPR4 */ + +#define OMAPL_PRUCORE_INTGPR4_REG_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTGPR4_REG_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTGPR4_REG_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTGPR4_RESETVAL (0x00000000u) + +/* INTGPR5 */ + +#define OMAPL_PRUCORE_INTGPR5_REG_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTGPR5_REG_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTGPR5_REG_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTGPR5_RESETVAL (0x00000000u) + +/* INTGPR6 */ + +#define OMAPL_PRUCORE_INTGPR6_REG_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTGPR6_REG_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTGPR6_REG_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTGPR6_RESETVAL (0x00000000u) + +/* INTGPR7 */ + +#define OMAPL_PRUCORE_INTGPR7_REG_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTGPR7_REG_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTGPR7_REG_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTGPR7_RESETVAL (0x00000000u) + +/* INTGPR8 */ + +#define OMAPL_PRUCORE_INTGPR8_REG_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTGPR8_REG_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTGPR8_REG_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTGPR8_RESETVAL (0x00000000u) + +/* INTGPR9 */ + +#define OMAPL_PRUCORE_INTGPR9_REG_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTGPR9_REG_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTGPR9_REG_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTGPR9_RESETVAL (0x00000000u) + +/* INTGPR10 */ + +#define OMAPL_PRUCORE_INTGPR10_REG_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTGPR10_REG_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTGPR10_REG_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTGPR10_RESETVAL (0x00000000u) + +/* INTGPR11 */ + +#define OMAPL_PRUCORE_INTGPR11_REG_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTGPR11_REG_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTGPR11_REG_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTGPR11_RESETVAL (0x00000000u) + +/* INTGPR12 */ + +#define OMAPL_PRUCORE_INTGPR12_REG_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTGPR12_REG_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTGPR12_REG_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTGPR12_RESETVAL (0x00000000u) + +/* INTGPR13 */ + +#define OMAPL_PRUCORE_INTGPR13_REG_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTGPR13_REG_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTGPR13_REG_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTGPR13_RESETVAL (0x00000000u) + +/* INTGPR14 */ + +#define OMAPL_PRUCORE_INTGPR14_REG_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTGPR14_REG_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTGPR14_REG_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTGPR14_RESETVAL (0x00000000u) + +/* INTGPR15 */ + +#define OMAPL_PRUCORE_INTGPR15_REG_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTGPR15_REG_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTGPR15_REG_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTGPR15_RESETVAL (0x00000000u) + +/* INTGPR16 */ + +#define OMAPL_PRUCORE_INTGPR16_REG_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTGPR16_REG_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTGPR16_REG_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTGPR16_RESETVAL (0x00000000u) + +/* INTGPR17 */ + +#define OMAPL_PRUCORE_INTGPR17_REG_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTGPR17_REG_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTGPR17_REG_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTGPR17_RESETVAL (0x00000000u) + +/* INTGPR18 */ + +#define OMAPL_PRUCORE_INTGPR18_REG_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTGPR18_REG_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTGPR18_REG_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTGPR18_RESETVAL (0x00000000u) + +/* INTGPR19 */ + +#define OMAPL_PRUCORE_INTGPR19_REG_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTGPR19_REG_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTGPR19_REG_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTGPR19_RESETVAL (0x00000000u) + +/* INTGPR20 */ + +#define OMAPL_PRUCORE_INTGPR20_REG_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTGPR20_REG_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTGPR20_REG_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTGPR20_RESETVAL (0x00000000u) + +/* INTGPR21 */ + +#define OMAPL_PRUCORE_INTGPR21_REG_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTGPR21_REG_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTGPR21_REG_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTGPR21_RESETVAL (0x00000000u) + +/* INTGPR22 */ + +#define OMAPL_PRUCORE_INTGPR22_REG_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTGPR22_REG_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTGPR22_REG_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTGPR22_RESETVAL (0x00000000u) + +/* INTGPR23 */ + +#define OMAPL_PRUCORE_INTGPR23_REG_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTGPR23_REG_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTGPR23_REG_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTGPR23_RESETVAL (0x00000000u) + +/* INTGPR24 */ + +#define OMAPL_PRUCORE_INTGPR24_REG_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTGPR24_REG_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTGPR24_REG_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTGPR24_RESETVAL (0x00000000u) + +/* INTGPR25 */ + +#define OMAPL_PRUCORE_INTGPR25_REG_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTGPR25_REG_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTGPR25_REG_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTGPR25_RESETVAL (0x00000000u) + +/* INTGPR26 */ + +#define OMAPL_PRUCORE_INTGPR26_REG_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTGPR26_REG_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTGPR26_REG_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTGPR26_RESETVAL (0x00000000u) + +/* INTGPR27 */ + +#define OMAPL_PRUCORE_INTGPR27_REG_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTGPR27_REG_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTGPR27_REG_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTGPR27_RESETVAL (0x00000000u) + +/* INTGPR28 */ + +#define OMAPL_PRUCORE_INTGPR28_REG_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTGPR28_REG_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTGPR28_REG_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTGPR28_RESETVAL (0x00000000u) + +/* INTGPR29 */ + +#define OMAPL_PRUCORE_INTGPR29_REG_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTGPR29_REG_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTGPR29_REG_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTGPR29_RESETVAL (0x00000000u) + +/* INTGPR30 */ + +#define OMAPL_PRUCORE_INTGPR30_REG_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTGPR30_REG_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTGPR30_REG_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTGPR30_RESETVAL (0x00000000u) + +/* INTGPR31 */ + +#define OMAPL_PRUCORE_INTGPR31_REG_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTGPR31_REG_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTGPR31_REG_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTGPR31_RESETVAL (0x00000000u) + +/* INTCTER0 */ + +#define OMAPL_PRUCORE_INTCTER0_ENTRY_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTCTER0_ENTRY_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTCTER0_ENTRY_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTCTER0_RESETVAL (0x00000000u) + +/* INTCTER1 */ + +#define OMAPL_PRUCORE_INTCTER1_ENTRY_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTCTER1_ENTRY_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTCTER1_ENTRY_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTCTER1_RESETVAL (0x00000000u) + +/* INTCTER2 */ + +#define OMAPL_PRUCORE_INTCTER2_ENTRY_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTCTER2_ENTRY_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTCTER2_ENTRY_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTCTER2_RESETVAL (0x00000000u) + +/* INTCTER3 */ + +#define OMAPL_PRUCORE_INTCTER3_ENTRY_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTCTER3_ENTRY_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTCTER3_ENTRY_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTCTER3_RESETVAL (0x00000000u) + +/* INTCTER4 */ + +#define OMAPL_PRUCORE_INTCTER4_ENTRY_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTCTER4_ENTRY_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTCTER4_ENTRY_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTCTER4_RESETVAL (0x00000000u) + +/* INTCTER5 */ + +#define OMAPL_PRUCORE_INTCTER5_ENTRY_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTCTER5_ENTRY_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTCTER5_ENTRY_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTCTER5_RESETVAL (0x00000000u) + +/* INTCTER6 */ + +#define OMAPL_PRUCORE_INTCTER6_ENTRY_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTCTER6_ENTRY_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTCTER6_ENTRY_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTCTER6_RESETVAL (0x00000000u) + +/* INTCTER7 */ + +#define OMAPL_PRUCORE_INTCTER7_ENTRY_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTCTER7_ENTRY_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTCTER7_ENTRY_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTCTER7_RESETVAL (0x00000000u) + +/* INTCTER8 */ + +#define OMAPL_PRUCORE_INTCTER8_ENTRY_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTCTER8_ENTRY_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTCTER8_ENTRY_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTCTER8_RESETVAL (0x00000000u) + +/* INTCTER9 */ + +#define OMAPL_PRUCORE_INTCTER9_ENTRY_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTCTER9_ENTRY_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTCTER9_ENTRY_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTCTER9_RESETVAL (0x00000000u) + +/* INTCTER10 */ + +#define OMAPL_PRUCORE_INTCTER10_ENTRY_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTCTER10_ENTRY_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTCTER10_ENTRY_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTCTER10_RESETVAL (0x00000000u) + +/* INTCTER11 */ + +#define OMAPL_PRUCORE_INTCTER11_ENTRY_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTCTER11_ENTRY_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTCTER11_ENTRY_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTCTER11_RESETVAL (0x00000000u) + +/* INTCTER12 */ + +#define OMAPL_PRUCORE_INTCTER12_ENTRY_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTCTER12_ENTRY_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTCTER12_ENTRY_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTCTER12_RESETVAL (0x00000000u) + +/* INTCTER13 */ + +#define OMAPL_PRUCORE_INTCTER13_ENTRY_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTCTER13_ENTRY_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTCTER13_ENTRY_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTCTER13_RESETVAL (0x00000000u) + +/* INTCTER14 */ + +#define OMAPL_PRUCORE_INTCTER14_ENTRY_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTCTER14_ENTRY_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTCTER14_ENTRY_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTCTER14_RESETVAL (0x00000000u) + +/* INTCTER15 */ + +#define OMAPL_PRUCORE_INTCTER15_ENTRY_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTCTER15_ENTRY_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTCTER15_ENTRY_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTCTER15_RESETVAL (0x00000000u) + +/* INTCTER16 */ + +#define OMAPL_PRUCORE_INTCTER16_ENTRY_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTCTER16_ENTRY_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTCTER16_ENTRY_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTCTER16_RESETVAL (0x00000000u) + +/* INTCTER17 */ + +#define OMAPL_PRUCORE_INTCTER17_ENTRY_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTCTER17_ENTRY_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTCTER17_ENTRY_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTCTER17_RESETVAL (0x00000000u) + +/* INTCTER18 */ + +#define OMAPL_PRUCORE_INTCTER18_ENTRY_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTCTER18_ENTRY_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTCTER18_ENTRY_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTCTER18_RESETVAL (0x00000000u) + +/* INTCTER19 */ + +#define OMAPL_PRUCORE_INTCTER19_ENTRY_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTCTER19_ENTRY_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTCTER19_ENTRY_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTCTER19_RESETVAL (0x00000000u) + +/* INTCTER20 */ + +#define OMAPL_PRUCORE_INTCTER20_ENTRY_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTCTER20_ENTRY_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTCTER20_ENTRY_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTCTER20_RESETVAL (0x00000000u) + +/* INTCTER21 */ + +#define OMAPL_PRUCORE_INTCTER21_ENTRY_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTCTER21_ENTRY_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTCTER21_ENTRY_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTCTER21_RESETVAL (0x00000000u) + +/* INTCTER22 */ + +#define OMAPL_PRUCORE_INTCTER22_ENTRY_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTCTER22_ENTRY_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTCTER22_ENTRY_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTCTER22_RESETVAL (0x00000000u) + +/* INTCTER23 */ + +#define OMAPL_PRUCORE_INTCTER23_ENTRY_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTCTER23_ENTRY_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTCTER23_ENTRY_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTCTER23_RESETVAL (0x00000000u) + +/* INTCTER24 */ + +#define OMAPL_PRUCORE_INTCTER24_ENTRY_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTCTER24_ENTRY_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTCTER24_ENTRY_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTCTER24_RESETVAL (0x00000000u) + +/* INTCTER25 */ + +#define OMAPL_PRUCORE_INTCTER25_ENTRY_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTCTER25_ENTRY_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTCTER25_ENTRY_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTCTER25_RESETVAL (0x00000000u) + +/* INTCTER26 */ + +#define OMAPL_PRUCORE_INTCTER26_ENTRY_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTCTER26_ENTRY_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTCTER26_ENTRY_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTCTER26_RESETVAL (0x00000000u) + +/* INTCTER27 */ + +#define OMAPL_PRUCORE_INTCTER27_ENTRY_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTCTER27_ENTRY_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTCTER27_ENTRY_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTCTER27_RESETVAL (0x00000000u) + +/* INTCTER28 */ + +#define OMAPL_PRUCORE_INTCTER28_ENTRY_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTCTER28_ENTRY_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTCTER28_ENTRY_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTCTER28_RESETVAL (0x00000000u) + +/* INTCTER29 */ + +#define OMAPL_PRUCORE_INTCTER29_ENTRY_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTCTER29_ENTRY_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTCTER29_ENTRY_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTCTER29_RESETVAL (0x00000000u) + +/* INTCTER30 */ + +#define OMAPL_PRUCORE_INTCTER30_ENTRY_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTCTER30_ENTRY_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTCTER30_ENTRY_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTCTER30_RESETVAL (0x00000000u) + +/* INTCTER31 */ + +#define OMAPL_PRUCORE_INTCTER31_ENTRY_MASK (0xFFFFFFFFu) +#define OMAPL_PRUCORE_INTCTER31_ENTRY_SHIFT (0x00000000u) +#define OMAPL_PRUCORE_INTCTER31_ENTRY_RESETVAL (0x00000000u) + +#define OMAPL_PRUCORE_INTCTER31_RESETVAL (0x00000000u) + + +/* Register Overlay Structure */ +typedef struct { + volatile u32 REVID; + volatile u8 RSVD0[20]; + volatile u32 INTEVAL; + volatile u8 RSVD1[36]; + volatile u32 MERRPR0; + volatile u8 RSVD2[12]; + volatile u32 MERRCR0; + volatile u8 RSVD3[12]; + volatile u32 PERRPR; + volatile u8 RSVD4[4]; + volatile u32 PERRCR; + volatile u8 RSVD5[180]; + volatile u32 PTCMD; + volatile u8 RSVD6[4]; + volatile u32 PTSTAT; + volatile u8 RSVD7[212]; + volatile u32 PDSTAT0; + volatile u32 PDSTAT1; + volatile u8 RSVD8[248]; + volatile u32 PDCTL0; + volatile u32 PDCTL1; + volatile u8 RSVD9[248]; + volatile u32 PDCFG0; + volatile u32 PDCFG1; + volatile u8 RSVD10[1016]; + volatile u32 MDSTAT[32]; + volatile u8 RSVD11[384]; + volatile u32 MDCTL[32]; +} OMAPL_PscRegs, *OMAPL_PscRegsOvly; + +/* Field Definition Macros */ + +/* REVID */ + +#define OMAPL_PSC_REVID_REV_MASK (0xFFFFFFFFu) +#define OMAPL_PSC_REVID_REV_SHIFT (0x00000000u) +#define OMAPL_PSC_REVID_REV_RESETVAL (0x44823A00u) + +#define OMAPL_PSC_REVID_RESETVAL (0x44823A00u) + +/* INTEVAL */ + +#define OMAPL_PSC_INTEVAL_ALLEV_MASK (0x00000001u) +#define OMAPL_PSC_INTEVAL_ALLEV_SHIFT (0x00000000u) +#define OMAPL_PSC_INTEVAL_ALLEV_RESETVAL (0x00000000u) +/*----ALLEV Tokens----*/ +#define OMAPL_PSC_INTEVAL_ALLEV_NO_EFFECT (0x00000000u) +#define OMAPL_PSC_INTEVAL_ALLEV_RE_EVALUATE (0x00000001u) + +#define OMAPL_PSC_INTEVAL_RESETVAL (0x00000000u) + +/* MERRPR0 */ + +#define OMAPL_PSC_MERRPR0_M15_MASK (0x0000C000u) +#define OMAPL_PSC_MERRPR0_M15_SHIFT (0x0000000Eu) +#define OMAPL_PSC_MERRPR0_M15_RESETVAL (0x00000000u) +/*----M15 Tokens----*/ +#define OMAPL_PSC_MERRPR0_M15_NO_ERR (0x00000000u) +#define OMAPL_PSC_MERRPR0_M15_ERROR (0x00000001u) + +#define OMAPL_PSC_MERRPR0_M14_MASK (0x00006000u) +#define OMAPL_PSC_MERRPR0_M14_SHIFT (0x0000000Du) +#define OMAPL_PSC_MERRPR0_M14_RESETVAL (0x00000000u) +/*----M14 Tokens----*/ +#define OMAPL_PSC_MERRPR0_M14_NO_ERR (0x00000000u) +#define OMAPL_PSC_MERRPR0_M14_ERROR (0x00000001u) + +#define OMAPL_PSC_MERRPR0_RESETVAL (0x00000000u) + +/* MERRCR0 */ + +#define OMAPL_PSC_MERRCR0_M15_MASK (0x0000C000u) +#define OMAPL_PSC_MERRCR0_M15_SHIFT (0x0000000Eu) +#define OMAPL_PSC_MERRCR0_M15_RESETVAL (0x00000000u) +/*----M15 Tokens----*/ +#define OMAPL_PSC_MERRCR0_M15_NO_EFFECT (0x00000000u) +#define OMAPL_PSC_MERRCR0_M15_CLR_ERR (0x00000001u) + +#define OMAPL_PSC_MERRCR0_M14_MASK (0x00006000u) +#define OMAPL_PSC_MERRCR0_M14_SHIFT (0x0000000Du) +#define OMAPL_PSC_MERRCR0_M14_RESETVAL (0x00000000u) +/*----M14 Tokens----*/ +#define OMAPL_PSC_MERRCR0_M14_NO_EFFECT (0x00000000u) +#define OMAPL_PSC_MERRCR0_M14_CLR_ERR (0x00000001u) + +#define OMAPL_PSC_MERRCR0_RESETVAL (0x00000000u) + +/* PERRPR */ + +#define OMAPL_PSC_PERRPR_P1_MASK (0x00000002u) +#define OMAPL_PSC_PERRPR_P1_SHIFT (0x00000001u) +#define OMAPL_PSC_PERRPR_P1_RESETVAL (0x00000000u) +/*----P1 Tokens----*/ +#define OMAPL_PSC_PERRPR_P1_NO_ERR (0x00000000u) +#define OMAPL_PSC_PERRPR_P1_ERROR (0x00000001u) + +#define OMAPL_PSC_PERRPR_P0_MASK (0x00000001u) +#define OMAPL_PSC_PERRPR_P0_SHIFT (0x00000000u) +#define OMAPL_PSC_PERRPR_P0_RESETVAL (0x00000000u) +/*----P0 Tokens----*/ +#define OMAPL_PSC_PERRPR_P0_NO_ERR (0x00000000u) +#define OMAPL_PSC_PERRPR_P0_ERROR (0x00000001u) + +#define OMAPL_PSC_PERRPR_RESETVAL (0x00000000u) + +/* PERRCR */ + +#define OMAPL_PSC_PERRCR_P1_MASK (0x00000002u) +#define OMAPL_PSC_PERRCR_P1_SHIFT (0x00000001u) +#define OMAPL_PSC_PERRCR_P1_RESETVAL (0x00000000u) +/*----P1 Tokens----*/ +#define OMAPL_PSC_PERRCR_P1_NO_EFFECT (0x00000000u) +#define OMAPL_PSC_PERRCR_P1_CLR_ERR (0x00000001u) + +#define OMAPL_PSC_PERRCR_P0_MASK (0x00000001u) +#define OMAPL_PSC_PERRCR_P0_SHIFT (0x00000000u) +#define OMAPL_PSC_PERRCR_P0_RESETVAL (0x00000000u) +/*----P0 Tokens----*/ +#define OMAPL_PSC_PERRCR_P0_NO_EFFECT (0x00000000u) +#define OMAPL_PSC_PERRCR_P0_CLR_ERR (0x00000001u) + +#define OMAPL_PSC_PERRCR_RESETVAL (0x00000000u) + +/* PTCMD */ + +#define OMAPL_PSC_PTCMD_GO1_MASK (0x00000002u) +#define OMAPL_PSC_PTCMD_GO1_SHIFT (0x00000001u) +#define OMAPL_PSC_PTCMD_GO1_RESETVAL (0x00000000u) +/*----GO1 Tokens----*/ +#define OMAPL_PSC_PTCMD_GO1_NO_EFFECT (0x00000000u) +#define OMAPL_PSC_PTCMD_GO1_SET (0x00000001u) + +#define OMAPL_PSC_PTCMD_GO0_MASK (0x00000001u) +#define OMAPL_PSC_PTCMD_GO0_SHIFT (0x00000000u) +#define OMAPL_PSC_PTCMD_GO0_RESETVAL (0x00000000u) +/*----GO0 Tokens----*/ +#define OMAPL_PSC_PTCMD_GO0_NO_EFFECT (0x00000000u) +#define OMAPL_PSC_PTCMD_GO0_SET (0x00000001u) + +#define OMAPL_PSC_PTCMD_RESETVAL (0x00000000u) + +/* PTSTAT */ + +#define OMAPL_PSC_PTSTAT_GOSTAT1_MASK (0x00000002u) +#define OMAPL_PSC_PTSTAT_GOSTAT1_SHIFT (0x00000001u) +#define OMAPL_PSC_PTSTAT_GOSTAT1_RESETVAL (0x00000000u) +/*----GOSTAT1 Tokens----*/ +#define OMAPL_PSC_PTSTAT_GOSTAT1_NO_TRANSITION (0x00000000u) +#define OMAPL_PSC_PTSTAT_GOSTAT1_IN_TRANSITION (0x00000001u) + +#define OMAPL_PSC_PTSTAT_GOSTAT0_MASK (0x00000001u) +#define OMAPL_PSC_PTSTAT_GOSTAT0_SHIFT (0x00000000u) +#define OMAPL_PSC_PTSTAT_GOSTAT0_RESETVAL (0x00000000u) +/*----GOSTAT0 Tokens----*/ +#define OMAPL_PSC_PTSTAT_GOSTAT0_NO_TRANSITION (0x00000000u) +#define OMAPL_PSC_PTSTAT_GOSTAT0_IN_TRANSITION (0x00000001u) + +#define OMAPL_PSC_PTSTAT_RESETVAL (0x00000000u) + +/* PDSTAT0 */ + +#define OMAPL_PSC_PDSTAT0_EMUIHB_MASK (0x00000800u) +#define OMAPL_PSC_PDSTAT0_EMUIHB_SHIFT (0x0000000Bu) +#define OMAPL_PSC_PDSTAT0_EMUIHB_RESETVAL (0x00000000u) +/*----EMUIHB Tokens----*/ +#define OMAPL_PSC_PDSTAT0_EMUIHB_INHIBIT_OFF (0x00000000u) +#define OMAPL_PSC_PDSTAT0_EMUIHB_INHIBIT_ON (0x00000001u) + +#define OMAPL_PSC_PDSTAT0_STATE_MASK (0x0000001Fu) +#define OMAPL_PSC_PDSTAT0_STATE_SHIFT (0x00000000u) +#define OMAPL_PSC_PDSTAT0_STATE_RESETVAL (0x00000000u) +/*----STATE Tokens----*/ +#define OMAPL_PSC_PDSTAT0_STATE_OFF (0x00000000u) +#define OMAPL_PSC_PDSTAT0_STATE_ON (0x00000001u) + +#define OMAPL_PSC_PDSTAT0_RESETVAL (0x00000000u) + +/* PDSTAT1 */ + +#define OMAPL_PSC_PDSTAT1_EMUIHB_MASK (0x00000800u) +#define OMAPL_PSC_PDSTAT1_EMUIHB_SHIFT (0x0000000Bu) +#define OMAPL_PSC_PDSTAT1_EMUIHB_RESETVAL (0x00000000u) +/*----EMUIHB Tokens----*/ +#define OMAPL_PSC_PDSTAT1_EMUIHB_INHIBIT_OFF (0x00000000u) +#define OMAPL_PSC_PDSTAT1_EMUIHB_INHIBIT_ON (0x00000001u) + +#define OMAPL_PSC_PDSTAT1_STATE_MASK (0x0000001Fu) +#define OMAPL_PSC_PDSTAT1_STATE_SHIFT (0x00000000u) +#define OMAPL_PSC_PDSTAT1_STATE_RESETVAL (0x00000000u) +/*----STATE Tokens----*/ +#define OMAPL_PSC_PDSTAT1_STATE_OFF (0x00000000u) +#define OMAPL_PSC_PDSTAT1_STATE_ON (0x00000001u) + +#define OMAPL_PSC_PDSTAT1_RESETVAL (0x00000000u) + +/* PDCTL0 */ + +#define OMAPL_PSC_PDCTL0_WAKECNT_MASK (0x00FF0000u) +#define OMAPL_PSC_PDCTL0_WAKECNT_SHIFT (0x00000010u) +#define OMAPL_PSC_PDCTL0_WAKECNT_RESETVAL (0x0000001Fu) + +#define OMAPL_PSC_PDCTL0_PDMODE_MASK (0x0000F000u) +#define OMAPL_PSC_PDCTL0_PDMODE_SHIFT (0x0000000Cu) +#define OMAPL_PSC_PDCTL0_PDMODE_RESETVAL (0x0000000Fu) + +#define OMAPL_PSC_PDCTL0_EMUIHBIE_MASK (0x00000200u) +#define OMAPL_PSC_PDCTL0_EMUIHBIE_SHIFT (0x00000009u) +#define OMAPL_PSC_PDCTL0_EMUIHBIE_RESETVAL (0x00000000u) +/*----EMUIHBIE Tokens----*/ +#define OMAPL_PSC_PDCTL0_EMUIHBIE_DISABLE (0x00000000u) +#define OMAPL_PSC_PDCTL0_EMUIHBIE_ENABLE (0x00000001u) + +#define OMAPL_PSC_PDCTL0_NEXT_MASK (0x00000001u) +#define OMAPL_PSC_PDCTL0_NEXT_SHIFT (0x00000000u) +#define OMAPL_PSC_PDCTL0_NEXT_RESETVAL (0x00000001u) +/*----NEXT Tokens----*/ +#define OMAPL_PSC_PDCTL0_NEXT_OFF (0x00000000u) +#define OMAPL_PSC_PDCTL0_NEXT_ON (0x00000001u) + +#define OMAPL_PSC_PDCTL0_RESETVAL (0x001FF101u) + +/* PDCTL1 */ + +#define OMAPL_PSC_PDCTL1_WAKECNT_MASK (0x00FF0000u) +#define OMAPL_PSC_PDCTL1_WAKECNT_SHIFT (0x00000010u) +#define OMAPL_PSC_PDCTL1_WAKECNT_RESETVAL (0x0000001Fu) + +#define OMAPL_PSC_PDCTL1_PDMODE_MASK (0x0000F000u) +#define OMAPL_PSC_PDCTL1_PDMODE_SHIFT (0x0000000Cu) +#define OMAPL_PSC_PDCTL1_PDMODE_RESETVAL (0x0000000Fu) +/*----PDMODE Tokens----*/ +#define OMAPL_PSC_PDCTL1_PDMODE_OFF (0x00000000u) +#define OMAPL_PSC_PDCTL1_PDMODE_RAM_OFF (0x00000008u) +#define OMAPL_PSC_PDCTL1_PDMODE_DEEP_SLEEP (0x00000009u) +#define OMAPL_PSC_PDCTL1_PDMODE_LIGHT_SLEEP (0x0000000Au) +#define OMAPL_PSC_PDCTL1_PDMODE_RETENTION (0x0000000Bu) +#define OMAPL_PSC_PDCTL1_PDMODE_ON (0x0000000Fu) + +#define OMAPL_PSC_PDCTL1_EMUIHBIE_MASK (0x00000200u) +#define OMAPL_PSC_PDCTL1_EMUIHBIE_SHIFT (0x00000009u) +#define OMAPL_PSC_PDCTL1_EMUIHBIE_RESETVAL (0x00000000u) +/*----EMUIHBIE Tokens----*/ +#define OMAPL_PSC_PDCTL1_EMUIHBIE_DISABLE (0x00000000u) +#define OMAPL_PSC_PDCTL1_EMUIHBIE_ENABLE (0x00000001u) + +#define OMAPL_PSC_PDCTL1_NEXT_MASK (0x00000001u) +#define OMAPL_PSC_PDCTL1_NEXT_SHIFT (0x00000000u) +#define OMAPL_PSC_PDCTL1_NEXT_RESETVAL (0x00000001u) +/*----NEXT Tokens----*/ +#define OMAPL_PSC_PDCTL1_NEXT_OFF (0x00000000u) +#define OMAPL_PSC_PDCTL1_NEXT_ON (0x00000001u) + +#define OMAPL_PSC_PDCTL1_RESETVAL (0x001FF101u) + +/* PDCFG0 */ + +#define OMAPL_PSC_PDCFG0_PDLOCK_MASK (0x00000008u) +#define OMAPL_PSC_PDCFG0_PDLOCK_SHIFT (0x00000003u) +#define OMAPL_PSC_PDCFG0_PDLOCK_RESETVAL (0x00000001u) +/*----PD LOCK Tokens----*/ +#define OMAPL_PSC_PDCFG0_PDLOCK_YES (0x00000000u) +#define OMAPL_PSC_PDCFG0_PDLOCK_NO (0x00000001u) + +#define OMAPL_PSC_PDCFG0_ICEPICK_MASK (0x00000004u) +#define OMAPL_PSC_PDCFG0_ICEPICK_SHIFT (0x00000002u) +#define OMAPL_PSC_PDCFG0_ICEPICK_RESETVAL (0x00000001u) +/*----ICEPICK Tokens----*/ +#define OMAPL_PSC_PDCFG0_ICEPICK_ABSENT (0x00000000u) +#define OMAPL_PSC_PDCFG0_ICEPICK_PRESENT (0x00000001u) + +#define OMAPL_PSC_PDCFG0_RAM_PSM_MASK (0x00000002u) +#define OMAPL_PSC_PDCFG0_RAM_PSM_SHIFT (0x00000001u) +#define OMAPL_PSC_PDCFG0_RAM_PSM_RESETVAL (0x00000000u) +/*----RAM_PSM Tokens----*/ +#define OMAPL_PSC_PDCFG0_RAM_PSM_NO (0x00000000u) +#define OMAPL_PSC_PDCFG0_RAM_PSM_YES (0x00000001u) + +#define OMAPL_PSC_PDCFG0_ALWAYSON_MASK (0x00000001u) +#define OMAPL_PSC_PDCFG0_ALWAYSON_SHIFT (0x00000000u) +#define OMAPL_PSC_PDCFG0_ALWAYSON_RESETVAL (0x00000001u) +/*----ALWAYSON Tokens----*/ +#define OMAPL_PSC_PDCFG0_ALWAYSON_NO (0x00000000u) +#define OMAPL_PSC_PDCFG0_ALWAYSON_YES (0x00000001u) + +#define OMAPL_PSC_PDCFG0_RESETVAL (0x0000000Du) + +/* PDCFG1 */ + +#define OMAPL_PSC_PDCFG1_PDLOCK_MASK (0x00000008u) +#define OMAPL_PSC_PDCFG1_PDLOCK_SHIFT (0x00000003u) +#define OMAPL_PSC_PDCFG1_PDLOCK_RESETVAL (0x00000001u) +/*----PD LOCK Tokens----*/ +#define OMAPL_PSC_PDCFG1_PDLOCK_YES (0x00000000u) +#define OMAPL_PSC_PDCFG1_PDLOCK_NO (0x00000001u) + +#define OMAPL_PSC_PDCFG1_ICEPICK_MASK (0x00000004u) +#define OMAPL_PSC_PDCFG1_ICEPICK_SHIFT (0x00000002u) +#define OMAPL_PSC_PDCFG1_ICEPICK_RESETVAL (0x00000001u) +/*----ICEPICK Tokens----*/ +#define OMAPL_PSC_PDCFG1_ICEPICK_ABSENT (0x00000000u) +#define OMAPL_PSC_PDCFG1_ICEPICK_PRESENT (0x00000001u) + +#define OMAPL_PSC_PDCFG1_RAM_PSM_MASK (0x00000002u) +#define OMAPL_PSC_PDCFG1_RAM_PSM_SHIFT (0x00000001u) +#define OMAPL_PSC_PDCFG1_RAM_PSM_RESETVAL (0x00000001u) +/*----RAM_PSM Tokens----*/ +#define OMAPL_PSC_PDCFG1_RAM_PSM_NO (0x00000000u) +#define OMAPL_PSC_PDCFG1_RAM_PSM_YES (0x00000001u) + +#define OMAPL_PSC_PDCFG1_ALWAYSON_MASK (0x00000001u) +#define OMAPL_PSC_PDCFG1_ALWAYSON_SHIFT (0x00000000u) +#define OMAPL_PSC_PDCFG1_ALWAYSON_RESETVAL (0x00000000u) +/*----ALWAYSON Tokens----*/ +#define OMAPL_PSC_PDCFG1_ALWAYSON_NO (0x00000000u) +#define OMAPL_PSC_PDCFG1_ALWAYSON_YES (0x00000001u) + +#define OMAPL_PSC_PDCFG1_RESETVAL (0x0000000Eu) + +/* MDSTAT */ + +#define OMAPL_PSC_MDSTAT_EMUIHB_MASK (0x00020000u) +#define OMAPL_PSC_MDSTAT_EMUIHB_SHIFT (0x00000011u) +#define OMAPL_PSC_MDSTAT_EMUIHB_RESETVAL (0x00000000u) +/*----EMUIHB Tokens----*/ +#define OMAPL_PSC_MDSTAT_EMUIHB_DISABLE (0x00000000u) +#define OMAPL_PSC_MDSTAT_EMUIHB_ENABLE (0x00000001u) + +#define OMAPL_PSC_MDSTAT_EMURST_MASK (0x00010000u) +#define OMAPL_PSC_MDSTAT_EMURST_SHIFT (0x00000010u) +#define OMAPL_PSC_MDSTAT_EMURST_RESETVAL (0x00000000u) +/*----EMURST Tokens----*/ +#define OMAPL_PSC_MDSTAT_EMURST_DISABLE (0x00000000u) +#define OMAPL_PSC_MDSTAT_EMURST_ENABLE (0x00000001u) + +#define OMAPL_PSC_MDSTAT_MCKOUT_MASK (0x00001000u) +#define OMAPL_PSC_MDSTAT_MCKOUT_SHIFT (0x0000000Cu) +#define OMAPL_PSC_MDSTAT_MCKOUT_RESETVAL (0x00000000u) +/*----MCKOUT Tokens----*/ +#define OMAPL_PSC_MDSTAT_MCKOUT_OFF (0x00000000u) +#define OMAPL_PSC_MDSTAT_MCKOUT_ON (0x00000001u) + +#define OMAPL_PSC_MDSTAT_MRSTDONE_MASK (0x00000800u) +#define OMAPL_PSC_MDSTAT_MRSTDONE_SHIFT (0x0000000Bu) +#define OMAPL_PSC_MDSTAT_MRSTDONE_RESETVAL (0x00000000u) +/*----MRSTDONE Tokens----*/ +#define OMAPL_PSC_MDSTAT_MRSTDONE_COMPLETE (0x00000000u) +#define OMAPL_PSC_MDSTAT_MRSTDONE_INCOMPLETE (0x00000001u) + +#define OMAPL_PSC_MDSTAT_MRST_MASK (0x00000400u) +#define OMAPL_PSC_MDSTAT_MRST_SHIFT (0x0000000Au) +#define OMAPL_PSC_MDSTAT_MRST_RESETVAL (0x00000000u) +/*----MRST Tokens----*/ +#define OMAPL_PSC_MDSTAT_MRST_ASSERT (0x00000000u) +#define OMAPL_PSC_MDSTAT_MRST_DEASSERT (0x00000001u) + +#define OMAPL_PSC_MDSTAT_LRSTDONE_MASK (0x00000200u) +#define OMAPL_PSC_MDSTAT_LRSTDONE_SHIFT (0x00000009u) +#define OMAPL_PSC_MDSTAT_LRSTDONE_RESETVAL (0x00000000u) +/*----LRSTDONE Tokens----*/ +#define OMAPL_PSC_MDSTAT_LRSTDONE_NOTDONE (0x00000000u) +#define OMAPL_PSC_MDSTAT_LRSTDONE_DONE (0x00000001u) + +#define OMAPL_PSC_MDSTAT_LRST_MASK (0x00000100u) +#define OMAPL_PSC_MDSTAT_LRST_SHIFT (0x00000008u) +#define OMAPL_PSC_MDSTAT_LRST_RESETVAL (0x00000000u) +/*----LRST Tokens----*/ +#define OMAPL_PSC_MDSTAT_LRST_ASSERT (0x00000000u) +#define OMAPL_PSC_MDSTAT_LRST_DEASSERT (0x00000001u) + +#define OMAPL_PSC_MDSTAT_STATE_MASK (0x0000003Fu) +#define OMAPL_PSC_MDSTAT_STATE_SHIFT (0x00000000u) +#define OMAPL_PSC_MDSTAT_STATE_RESETVAL (0x00000000u) +/*----STATE Tokens----*/ +#define OMAPL_PSC_MDSTAT_STATE_SWRSTDISABLE (0x00000000u) +#define OMAPL_PSC_MDSTAT_STATE_SYNCRST (0x00000001u) +#define OMAPL_PSC_MDSTAT_STATE_DISABLE (0x00000002u) +#define OMAPL_PSC_MDSTAT_STATE_ENABLE (0x00000003u) +#define OMAPL_PSC_MDSTAT_STATE_AUTOSLEEP (0x00000004u) +#define OMAPL_PSC_MDSTAT_STATE_AUTOWAKE (0x00000005u) + +#define OMAPL_PSC_MDSTAT_RESETVAL (0x00000000u) + +/* MDCTL */ + +#define OMAPL_PSC_MDCTL_FORCE_MASK (0x80000000u) +#define OMAPL_PSC_MDCTL_FORCE_SHIFT (0x0000001Fu) +#define OMAPL_PSC_MDCTL_FORCE_RESETVAL (0x00000000u) +/*----FORCE Tokens----*/ +#define OMAPL_PSC_MDCTL_FORCE_DISABLE (0x00000000u) +#define OMAPL_PSC_MDCTL_FORCE_ENABLE (0x00000001u) + +#define OMAPL_PSC_MDCTL_EMUIHBIE_MASK (0x00000400u) +#define OMAPL_PSC_MDCTL_EMUIHBIE_SHIFT (0x0000000Au) +#define OMAPL_PSC_MDCTL_EMUIHBIE_RESETVAL (0x00000000u) +/*----EMUIHBIE Tokens----*/ +#define OMAPL_PSC_MDCTL_EMUIHBIE_DISABLE (0x00000000u) +#define OMAPL_PSC_MDCTL_EMUIHBIE_ENABLE (0x00000001u) + +#define OMAPL_PSC_MDCTL_EMURSTIE_MASK (0x00000200u) +#define OMAPL_PSC_MDCTL_EMURSTIE_SHIFT (0x00000009u) +#define OMAPL_PSC_MDCTL_EMURSTIE_RESETVAL (0x00000000u) +/*----EMURSTIE Tokens----*/ +#define OMAPL_PSC_MDCTL_EMURSTIE_DISABLE (0x00000000u) +#define OMAPL_PSC_MDCTL_EMURSTIE_ENABLE (0x00000001u) + +#define OMAPL_PSC_MDCTL_LRST_MASK (0x00000100u) +#define OMAPL_PSC_MDCTL_LRST_SHIFT (0x00000008u) +#define OMAPL_PSC_MDCTL_LRST_RESETVAL (0x00000000u) +/*----LRST Tokens----*/ +#define OMAPL_PSC_MDCTL_LRST_ASSERT (0x00000000u) +#define OMAPL_PSC_MDCTL_LRST_DEASSERT (0x00000001u) + +#define OMAPL_PSC_MDCTL_NEXT_MASK (0x0000001Fu) +#define OMAPL_PSC_MDCTL_NEXT_SHIFT (0x00000000u) +#define OMAPL_PSC_MDCTL_NEXT_RESETVAL (0x00000000u) +/*----NEXT Tokens----*/ +#define OMAPL_PSC_MDCTL_NEXT_SWRSTDISABLE (0x00000000u) +#define OMAPL_PSC_MDCTL_NEXT_SYNCRST (0x00000001u) +#define OMAPL_PSC_MDCTL_NEXT_DISABLE (0x00000002u) +#define OMAPL_PSC_MDCTL_NEXT_ENABLE (0x00000003u) +#define OMAPL_PSC_MDCTL_NEXT_AUTOSLEEP (0x00000004u) +#define OMAPL_PSC_MDCTL_NEXT_AUTOWAKE (0x00000005u) + +#define OMAPL_PSC_MDCTL_RESETVAL (0x00000000u) + + +/* + * pru_can_enable() Configure and Enable PRU0 and PRU1 of OMAP L138. + * This API will be called by the Application to + * Configure and Enable PRU0 and PRU1 + */ +s16 pru_can_enable(void); + +/* + * pru_can_disable() Disable PRU0 and PRU1 of OMAP L138. + * This API will be called by the Application to + * disable PRU0 and PRU1 + */ +s16 pru_can_disable(void); + +/* + * pru_can_run () Allows the PRU0 or PRU1 of OMAP L138 to execute + * This API will be called by the Application to + * execute the instruction in PRU + */ +s16 pru_can_run(u8 u8prunum); + +/* + * pru_can_psc_enable () Enable state transition of PRU + * This API will be called by the Application + * for state transition of PRU + */ +s16 pru_can_psc_enable(void); + +/* + * pru_can_psc_disable () Disable state transition of PRU + * This API will be called by the Application + * disabling state transition of PRU + */ +s16 pru_can_psc_disable(void); + +/* + * pru_can_ram_write_data() Download the data to + * data RAM of PRU + */ +s16 pru_can_ram_write_data(u32 u32offset, + u32 *pu32datatowrite, u16 u16wordstowrite); +/* + * pru_can_ram_read_data() Download the data into data RAM. + */ +s16 pru_can_ram_read_data(u32 u32offset, + u32 *pu32datatoread, u16 u16wordstoread); + +/* + * pru_can_download_firmware() Download the firmware + */ +s16 pru_can_download_firmware(pru_can_firmware_structure *pstrfirmwaredata, + u8 u8prunum); + +/* + * pru_can_set_brp() Updates the BRP register of PRU. + */ +s16 pru_can_set_brp(u16 u16bitrateprescaler); + +/* + * pru_can_set_bit_timing() Updates the timing register of PRU + */ +s16 pru_can_set_bit_timing(can_bit_timing_consts *pstrcanbittiming); + +/* + * pru_can_calculatetiming() Updates the timing values of PRU + */ +s16 pru_can_calculatetiming(u32 u32canbittiming, u32 u32bitrateprescaler); + +/* + * pru_can_write_data_to_mailbox() Updates the transmit mailboxes of PRU1 + */ +s16 pru_can_write_data_to_mailbox(can_emulation_app_hndl *pstrcanemuapphndl); + +/* + * pru_can_get_data_from_mailbox() Receive data from receive mailboxes + */ +s16 pru_can_get_data_from_mailbox(can_emulation_app_hndl *pstrcanemuapphndl); + +/* + * pru_can_receive_id_map()Receive mailboxes ID Mapping of PRU0 + */ +s16 pru_can_receive_id_map(u32 u32nodeid, can_mailbox_number ecanmailboxno); + +/* + *pru_can_get_interrupt_status() Get interrupts status register value + */ +s16 pru_can_get_interrupt_status(can_emulation_app_hndl *pstrcanemuapphndl); + + +/* + * pru_can_get_global_status() Get the globalstatus register value + */ +s16 pru_can_get_global_status(can_emulation_app_hndl *pstrcanemuapphndl); + +/* + * pru_can_get_mailbox_status() Get mailbox status reg value + */ +s16 pru_can_get_mailbox_status(can_emulation_app_hndl *pstrcanemuapphndl); + +/* + * pru_can_configuration_mode_set() Sets timing val for data transfer + */ +s16 pru_can_configuration_mode_set(bool bconfigmodeenabledisableflag); + +/* + * pru_can_emulation_init() Initializes Can Emulation Parameters + */ +s16 pru_can_emulation_init(arm_pru_iomap *pstr_pru_iomap, u32 u32pruclock); + +/* + * pru_can_emulation_open() Opens can emulation for application to use + */ +s16 pru_can_emulation_open(can_emulation_app_hndl *pstrcanemuapphndl); + +/* + * pru_can_emulation_close() Closes can emulation for applications to use + */ +s16 pru_can_emulation_close(can_emulation_app_hndl *pstrcanemuapphndl); + +/* + * pru_can_emulation_exit() Diables all the PRUs + */ +s16 pru_can_emulation_exit(void); + +s16 pru_can_transfer_mode_set(bool btransfer_flag, + can_transfer_direction ecan_trx); + +s16 pru_can_emulation_sreset(void); + +s16 pru_can_transfer(u8 u8mailboxnumber, u8 u8prunumber); + +s16 pru_can_start_or_abort_transmission(bool bcantransmitabortflag); + +s16 pru_can_check_init_status(void); + +s16 pru_can_mask_ints(u32 int_mask); + +s32 pru_can_get_error_cnt(u8 u8prunumber); + +s32 pru_can_intc_status_get(void); +#endif diff --git a/drivers/net/can/omapl_pru/ti_omapl_pru_can.c b/drivers/net/can/omapl_pru/ti_omapl_pru_can.c new file mode 100644 index 0000000..51d14ab --- /dev/null +++ b/drivers/net/can/omapl_pru/ti_omapl_pru_can.c @@ -0,0 +1,827 @@ +/* + * TI OMAPL PRU CAN Emulation device driver + * Author: subhasish@mistralsolutions.com + * + * This driver supports TI's PRU CAN Emulation and the + * specs for the same is available at <http://www.ti.com> + * + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed as is WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/bitops.h> +#include <linux/interrupt.h> +#include <linux/errno.h> +#include <linux/netdevice.h> +#include <linux/skbuff.h> +#include <linux/platform_device.h> +#include <linux/firmware.h> +#include <linux/clk.h> +#include <linux/types.h> + +#include <linux/can.h> +#include <linux/can/dev.h> +#include <linux/can/error.h> +#include <mach/da8xx.h> +#include "pru_can_api.h" + +#define DRV_NAME "davinci_pru_can" +#define DRV_DESC "TI PRU CAN Controller Driver v0.1" +#define PRU_CAN_START 1 +#define PRU_CAN_STOP 0 +#define MB_MIN 0 +#define MB_MAX 7 +#define CAN_RX_PRU_0 OMAPL_PRUCORE_0 +#define CAN_TX_PRU_1 OMAPL_PRUCORE_1 + +#define PRU_CANMID_IDE BIT(29) /* Extended frame format */ + +#define PRU_CAN_ISR_BIT_CCI BIT(15) +#define PRU_CAN_ISR_BIT_ESI BIT(14) +#define PRU_CAN_ISR_BIT_SRDI BIT(13) +#define PRU_CAN_ISR_BIT_RRI BIT(8) + +#define PRU_CAN_MBXSR_BIT_STATE BIT(7) +#define PRU_CAN_MBXSR_BIT_TC BIT(6) +#define PRU_CAN_MBXSR_BIT_ERR BIT(5) +#define PRU_CAN_MBXSR_BIT_OF BIT(0) + +#define PRU_CAN_GSR_BIT_TXM BIT(7) +#define PRU_CAN_GSR_BIT_RXM BIT(6) +#define PRU_CAN_GSR_BIT_CM BIT(5) +#define PRU_CAN_GSR_BIT_EPM BIT(4) +#define PRU_CAN_GSR_BIT_BFM BIT(3) +#define RTR_MBX_NO 8 +#define MAX_INIT_RETRIES 20 +#define L138_PRU_ARM_FREQ 312000 +#define DFLT_PRU_FREQ 156000000 +#define DFLT_PRU_BITRATE 125000 + +#define CONFIG_OMAPL_PRU_CANID_MBX0 0x123 +#define CONFIG_OMAPL_PRU_CANID_MBX1 0x123 +#define CONFIG_OMAPL_PRU_CANID_MBX2 0x123 +#define CONFIG_OMAPL_PRU_CANID_MBX3 0x123 +#define CONFIG_OMAPL_PRU_CANID_MBX4 0x123 +#define CONFIG_OMAPL_PRU_CANID_MBX5 0x123 +#define CONFIG_OMAPL_PRU_CANID_MBX6 0x123 +#define CONFIG_OMAPL_PRU_CANID_MBX7 0x123 + +#ifdef __CAN_DEBUG +#define __can_debug(fmt, args...) printk(KERN_DEBUG "can_debug: " fmt, ## args) +#else +#define __can_debug(fmt, args...) +#endif +#define __can_err(fmt, args...) printk(KERN_ERR "can_err: " fmt, ## args) + +/* + * omapl_pru can private data + */ +struct omapl_pru_can_priv { + struct can_priv can; /* must be the first member,can_priv = netdev_priv(ndev) */ + struct workqueue_struct *pru_can_wQ; + struct work_struct rx_work; + struct net_device *ndev; + struct clk *clk; + struct clk *clk_timer; + u32 timer_freq; + arm_pru_iomap pru_arm_iomap; + can_emulation_app_hndl can_tx_hndl; + can_emulation_app_hndl can_rx_hndl; + const struct firmware *fw_rx; + const struct firmware *fw_tx; + spinlock_t mbox_lock; + u32 trx_irq; + u32 tx_head; + u32 tx_tail; + u32 tx_next; + u32 rx_next; +}; + +static int omapl_pru_can_get_state(const struct net_device *ndev, + enum can_state *state) +{ + struct omapl_pru_can_priv *priv = netdev_priv(ndev); + *state = priv->can.state; + return 0; +} + +static int omapl_pru_can_set_bittiming(struct net_device *dev) +{ + struct omapl_pru_can_priv *priv = netdev_priv(dev); + struct can_bittiming *bt = &priv->can.bittiming; + long bit_error = 0; + + if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) { + dev_warn(priv->ndev->dev.parent, "WARN: Triple" + "sampling not set due to h/w limitations"); + } + if (pru_can_calculatetiming(priv->can.clock.freq, bt->bitrate) != 0) + return -EINVAL; + bit_error = + (((priv->timer_freq / (priv->timer_freq / bt->bitrate)) - + bt->bitrate) * 1000) / bt->bitrate; + if (bit_error) { + bit_error = + (((priv->timer_freq / (priv->timer_freq / bt->bitrate)) - + bt->bitrate) * 1000000) / bt->bitrate; + printk(KERN_INFO "\nBitrate error %ld.%ld%%\n", + bit_error / 10000, bit_error % 1000); + } else + printk(KERN_INFO "\nBitrate error 0.0%%\n"); + + return 0; +} + +static void omapl_pru_can_stop(struct net_device *ndev) +{ + struct omapl_pru_can_priv *priv = netdev_priv(ndev); + u16 int_mask = 0; + + pru_can_mask_ints(int_mask); /* mask all ints */ + pru_can_start_or_abort_transmission(PRU_CAN_STOP); + priv->can.state = CAN_STATE_STOPPED; +} + +/* + * This is to just set the can state to ERROR_ACTIVE + * ip link set canX up type can bitrate 125000 + */ +static void omapl_pru_can_start(struct net_device *ndev) +{ + struct omapl_pru_can_priv *priv = netdev_priv(ndev); + u16 int_mask = 0xFFFF; + + if (priv->can.state != CAN_STATE_STOPPED) + omapl_pru_can_stop(ndev); + + pru_can_mask_ints(int_mask); /* unmask all ints */ + + pru_can_get_global_status(&priv->can_tx_hndl); + pru_can_get_global_status(&priv->can_rx_hndl); + + if (PRU_CAN_GSR_BIT_EPM & priv->can_tx_hndl.u32globalstatus) + priv->can.state = CAN_STATE_ERROR_PASSIVE; + else if (PRU_CAN_GSR_BIT_BFM & priv->can_tx_hndl.u32globalstatus) + priv->can.state = CAN_STATE_BUS_OFF; + else + priv->can.state = CAN_STATE_ERROR_ACTIVE; +} + +static int omapl_pru_can_set_mode(struct net_device *ndev, enum can_mode mode) +{ + int ret = 0; + + switch (mode) { + case CAN_MODE_START: + omapl_pru_can_start(ndev); + if (netif_queue_stopped(ndev)) + netif_wake_queue(ndev); + break; + case CAN_MODE_STOP: + omapl_pru_can_stop(ndev); + if (!netif_queue_stopped(ndev)) + netif_stop_queue(ndev); + break; + default: + ret = -EOPNOTSUPP; + break; + } + return ret; +} + +static netdev_tx_t omapl_pru_can_start_xmit(struct sk_buff *skb, + struct net_device *ndev) +{ + struct omapl_pru_can_priv *priv = netdev_priv(ndev); + struct can_frame *cf = (struct can_frame *)skb->data; + int count; + u8 *data = cf->data; + u8 dlc = cf->can_dlc; + u8 *ptr8data = NULL; + + netif_stop_queue(ndev); + if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */ + *((u32 *) &priv->can_tx_hndl.strcanmailbox) = + (cf->can_id & CAN_EFF_MASK) | PRU_CANMID_IDE; + else /* Standard frame format */ + *((u32 *) &priv->can_tx_hndl.strcanmailbox) = + (cf->can_id & CAN_SFF_MASK) << 18; + + if (cf->can_id & CAN_RTR_FLAG) /* Remote transmission request */ + *((u32 *) &priv->can_tx_hndl.strcanmailbox) |= CAN_RTR_FLAG; + + ptr8data = &priv->can_tx_hndl.strcanmailbox.u8data7 + (dlc - 1); + for (count = 0; count < (u8) dlc; count++) { + *ptr8data-- = *data++; + } + *((u32 *) &priv->can_tx_hndl.strcanmailbox.u16datalength) = (u32) dlc; +/* + * search for the next available mbx + * if the next mbx is busy, then try the next + 1 + * do this until the head is reached. + * if still unable to tx, stop accepting any packets + * if able to tx and the head is reached, then reset next to tail, i.e mbx0 + * if head is not reached, then just point to the next mbx + */ + for (; priv->tx_next <= priv->tx_head; priv->tx_next++) { + priv->can_tx_hndl.ecanmailboxnumber = + (can_mailbox_number) priv->tx_next; + if (-1 == pru_can_write_data_to_mailbox(&priv->can_tx_hndl)) { + if (priv->tx_next == priv->tx_head) { + priv->tx_next = priv->tx_tail; + if (!netif_queue_stopped(ndev)) + netif_stop_queue(ndev); /* IF stalled */ + dev_err(priv->ndev->dev.parent, + "%s: no tx mbx available", __func__); + return NETDEV_TX_BUSY; + } else + continue; + } else { + /* set transmit request */ + pru_can_transfer(priv->tx_next, CAN_TX_PRU_1); + pru_can_transfer_mode_set(false, ecanreceive); + pru_can_transfer_mode_set(true, ecantransmit); + pru_can_start_or_abort_transmission(PRU_CAN_START); + priv->tx_next++; + can_put_echo_skb(skb, ndev, 0); + break; + } + } + if (priv->tx_next > priv->tx_head) { + priv->tx_next = priv->tx_tail; + } + return NETDEV_TX_OK; +} + +static int omapl_pru_can_rx(struct net_device *ndev, u32 mbxno) +{ + struct omapl_pru_can_priv *priv = netdev_priv(ndev); + struct net_device_stats *stats = &ndev->stats; + struct can_frame *cf; + struct sk_buff *skb; + u32 pru_can_mbx_data; + u8 *data = NULL; + u8 *ptr8data = NULL; + int count = 0; + + skb = alloc_can_skb(ndev, &cf); + if (!skb) { + if (printk_ratelimit()) + dev_err(priv->ndev->dev.parent, + "ti_pru_can_rx_pkt: alloc_can_skb() failed\n"); + return -ENOMEM; + } + data = cf->data; + /* get payload */ + priv->can_rx_hndl.ecanmailboxnumber = (can_mailbox_number) mbxno; + if (pru_can_get_data_from_mailbox(&priv->can_rx_hndl)) { + __can_err("pru_can_get_data_from_mailbox: failed\n"); + return -EAGAIN; + } + /* give ownweship to pru */ + pru_can_transfer(mbxno, CAN_RX_PRU_0); + + /* get data length code */ + cf->can_dlc = + get_can_dlc(* + ((u32 *) &priv->can_rx_hndl.strcanmailbox. + u16datalength) & 0xF); + if (cf->can_dlc <= 4) { + ptr8data = + &priv->can_rx_hndl.strcanmailbox.u8data3 + (4 - + cf->can_dlc); + for (count = 0; count < cf->can_dlc; count++) { + *data++ = *ptr8data++; + } + } else { + ptr8data = &priv->can_rx_hndl.strcanmailbox.u8data3; + for (count = 0; count < 4; count++) { + *data++ = *ptr8data++; + } + ptr8data = + &priv->can_rx_hndl.strcanmailbox.u8data4 - (cf->can_dlc - + 5); + for (count = 0; count < cf->can_dlc - 4; count++) { + *data++ = *ptr8data++; + } + } + + pru_can_mbx_data = *((u32 *) &priv->can_rx_hndl.strcanmailbox); + /* get id extended or std */ + if (pru_can_mbx_data & PRU_CANMID_IDE) + cf->can_id = (pru_can_mbx_data & CAN_EFF_MASK) | CAN_EFF_FLAG; + else + cf->can_id = (pru_can_mbx_data >> 18) & CAN_SFF_MASK; + + if (pru_can_mbx_data & CAN_RTR_FLAG) + cf->can_id |= CAN_RTR_FLAG; + + netif_rx_ni(skb); + stats->rx_packets++; + stats->rx_bytes += cf->can_dlc; + return 0; +} + +static int omapl_pru_can_err(struct net_device *ndev, int int_status, + int err_status) +{ + struct omapl_pru_can_priv *priv = netdev_priv(ndev); + struct net_device_stats *stats = &ndev->stats; + struct can_frame *cf; + struct sk_buff *skb; + int tx_err_cnt, rx_err_cnt; + + /* propogate the error condition to the can stack */ + skb = alloc_can_err_skb(ndev, &cf); + if (!skb) { + if (printk_ratelimit()) + dev_err(priv->ndev->dev.parent, + "omapl_pru_can_err: alloc_can_err_skb() failed\n"); + return -ENOMEM; + } + + if (err_status & PRU_CAN_GSR_BIT_EPM) { /* error passive int */ + priv->can.state = CAN_STATE_ERROR_PASSIVE; + ++priv->can.can_stats.error_passive; + cf->can_id |= CAN_ERR_CRTL; + tx_err_cnt = pru_can_get_error_cnt(CAN_TX_PRU_1); + rx_err_cnt = pru_can_get_error_cnt(CAN_RX_PRU_0); + if (tx_err_cnt > 127) + cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; + if (rx_err_cnt > 127) + cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; + + dev_dbg(priv->ndev->dev.parent, "Error passive interrupt\n"); + } + + if (err_status & PRU_CAN_GSR_BIT_BFM) { + priv->can.state = CAN_STATE_BUS_OFF; + cf->can_id |= CAN_ERR_BUSOFF; + /* + * Disable all interrupts in bus-off to avoid int hog + * this should be handled by the pru + */ + pru_can_mask_ints(0xFFFF); + can_bus_off(ndev); + dev_dbg(priv->ndev->dev.parent, "Bus off mode\n"); + } + + netif_rx(skb); + stats->rx_packets++; + stats->rx_bytes += cf->can_dlc; + return 0; +} + +void omapl_pru_can_rx_wQ(struct work_struct *work) +{ + struct omapl_pru_can_priv *priv = container_of(work, + struct + omapl_pru_can_priv, + rx_work); + struct net_device *ndev = priv->ndev; + u32 bit_set, mbxno = 0; + + if (-1 == pru_can_get_interrupt_status(&priv->can_rx_hndl)) + return; + + if (PRU_CAN_ISR_BIT_RRI & priv->can_rx_hndl.u32interruptstatus) { + mbxno = RTR_MBX_NO; + omapl_pru_can_rx(ndev, mbxno); + } else { + /* Extract the mboxno from the status */ + for (bit_set = 0; ((priv->can_rx_hndl.u32interruptstatus & 0xFF) + >> bit_set != 0); bit_set++) + ; + if (0 == bit_set) { + dev_err(ndev->dev.parent, + "%s: invalid mailbox number: %X\n", __func__, + priv->can_rx_hndl.u32interruptstatus); + } else { + mbxno = bit_set - 1; /* mail box numbering starts from 0 */ + if (PRU_CAN_ISR_BIT_ESI & priv->can_rx_hndl. + u32interruptstatus) { + pru_can_get_global_status(&priv->can_rx_hndl); + omapl_pru_can_err(ndev, + priv->can_rx_hndl. + u32interruptstatus, + priv->can_rx_hndl. + u32globalstatus); + } else { + omapl_pru_can_rx(ndev, mbxno); + } + } + } +} + +irqreturn_t omapl_tx_can_intr(int irq, void *dev_id) +{ + struct net_device *ndev = dev_id; + struct omapl_pru_can_priv *priv = netdev_priv(ndev); + struct net_device_stats *stats = &ndev->stats; + u32 bit_set, mbxno; + + pru_can_get_interrupt_status(&priv->can_tx_hndl); + if ((PRU_CAN_ISR_BIT_CCI & priv->can_tx_hndl.u32interruptstatus) + || (PRU_CAN_ISR_BIT_SRDI & priv->can_tx_hndl.u32interruptstatus)) { + __can_debug("tx_int_status = 0x%X\n", + priv->can_tx_hndl.u32interruptstatus); + can_free_echo_skb(ndev, 0); + } else { + for (bit_set = 0; ((priv->can_tx_hndl.u32interruptstatus & 0xFF) + >> bit_set != 0); bit_set++) + ; + if (0 == bit_set) { + __can_err("%s: invalid mailbox number\n", __func__); + can_free_echo_skb(ndev, 0); + } else { + mbxno = bit_set - 1; /* mail box numbering starts from 0 */ + if (PRU_CAN_ISR_BIT_ESI & priv->can_tx_hndl. + u32interruptstatus) { + /* read gsr and ack pru */ + pru_can_get_global_status(&priv->can_tx_hndl); + omapl_pru_can_err(ndev, + priv->can_tx_hndl. + u32interruptstatus, + priv->can_tx_hndl. + u32globalstatus); + } else { + stats->tx_packets++; + /* stats->tx_bytes += dlc; */ + /*can_get_echo_skb(ndev, 0);*/ + } + } + } + if (netif_queue_stopped(ndev)) + netif_wake_queue(ndev); + + can_get_echo_skb(ndev, 0); + pru_can_transfer_mode_set(true, ecanreceive); + return IRQ_HANDLED; +} + +irqreturn_t omapl_rx_can_intr(int irq, void *dev_id) +{ + + struct net_device *ndev = dev_id; + struct omapl_pru_can_priv *priv = netdev_priv(ndev); + u32 intc_status = 0; + + intc_status = pru_can_intc_status_get(); + if (intc_status & 4) + return omapl_tx_can_intr(irq, dev_id); + if (intc_status & 2) { + if (!work_pending(&priv->rx_work)) + queue_work(priv->pru_can_wQ, &priv->rx_work); + } + + return IRQ_HANDLED; +} + +static int omapl_pru_can_open(struct net_device *ndev) +{ + struct omapl_pru_can_priv *priv = netdev_priv(ndev); + int err; + + /* register interrupt handler */ + err = request_irq(priv->trx_irq, &omapl_rx_can_intr, IRQF_SHARED, + "pru_can_irq", ndev); + if (err) { + dev_err(ndev->dev.parent, "error requesting rx interrupt\n"); + goto exit_trx_irq; + } + /* common open */ + err = open_candev(ndev); + if (err) { + dev_err(ndev->dev.parent, "open_candev() failed %d\n", err); + goto exit_open; + } + + pru_can_emulation_init(&priv->pru_arm_iomap, priv->can.clock.freq); + priv->tx_tail = MB_MIN; + priv->tx_head = MB_MAX; + + pru_can_receive_id_map(CONFIG_OMAPL_PRU_CANID_MBX0, 0); + pru_can_receive_id_map(CONFIG_OMAPL_PRU_CANID_MBX1, 1); + pru_can_receive_id_map(CONFIG_OMAPL_PRU_CANID_MBX2, 2); + pru_can_receive_id_map(CONFIG_OMAPL_PRU_CANID_MBX3, 3); + pru_can_receive_id_map(CONFIG_OMAPL_PRU_CANID_MBX4, 4); + pru_can_receive_id_map(CONFIG_OMAPL_PRU_CANID_MBX5, 5); + pru_can_receive_id_map(CONFIG_OMAPL_PRU_CANID_MBX6, 6); + pru_can_receive_id_map(CONFIG_OMAPL_PRU_CANID_MBX7, 7); + + omapl_pru_can_start(ndev); + netif_start_queue(ndev); + return 0; + +exit_open: + free_irq(priv->trx_irq, ndev); +exit_trx_irq: + return err; +} + +static int omapl_pru_can_close(struct net_device *ndev) +{ + struct omapl_pru_can_priv *priv = netdev_priv(ndev); + + if (!netif_queue_stopped(ndev)) + netif_stop_queue(ndev); + + close_candev(ndev); + + free_irq(priv->trx_irq, ndev); + clk_disable(priv->clk); + + return 0; +} + +static const struct net_device_ops omapl_pru_can_netdev_ops = { + .ndo_open = omapl_pru_can_open, + .ndo_stop = omapl_pru_can_close, + .ndo_start_xmit = omapl_pru_can_start_xmit, +}; + +static int __devinit omapl_pru_can_probe(struct platform_device *pdev) +{ + struct net_device *ndev = NULL; + struct omapl_pru_can_priv *priv = NULL; + struct resource *res_mem, *trx_irq; + pru_can_firmware_structure fw_pru; + u32 err, retries = 0; + + res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res_mem) { + dev_err(&pdev->dev, "unable to get pru memory resources!\n"); + err = -ENODEV; + goto probe_exit; + } + + trx_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!trx_irq) { + dev_err(&pdev->dev, "unable to get pru interrupt resources!\n"); + err = -ENODEV; + goto probe_exit; + } + + if (!request_mem_region(res_mem->start, resource_size(res_mem), + dev_name(&pdev->dev))) { + dev_err(&pdev->dev, "pru memory region already claimed!\n"); + err = -EBUSY; + goto probe_exit; + } + + ndev = alloc_candev(sizeof(struct omapl_pru_can_priv), MB_MAX + 1); + if (!ndev) { + dev_err(&pdev->dev, "alloc_candev failed\n"); + err = -ENOMEM; + goto probe_exit_free_region; + } + priv = netdev_priv(ndev); + + priv->pru_arm_iomap.pru_io_addr = + ioremap(res_mem->start, resource_size(res_mem)); + if (!priv->pru_arm_iomap.pru_io_addr) { + dev_err(&pdev->dev, "ioremap failed\n"); + err = -ENOMEM; + goto probe_exit_free_region; + } + + priv->pru_arm_iomap.psc0_io_addr = IO_ADDRESS(DA8XX_PSC0_BASE); + if (!priv->pru_arm_iomap.psc0_io_addr) { + dev_err(&pdev->dev, "ioremap failed\n"); + err = -ENOMEM; + goto probe_exit_iounmap; + } + + priv->pru_arm_iomap.psc1_io_addr = IO_ADDRESS(DA8XX_PSC1_BASE); + if (!priv->pru_arm_iomap.psc1_io_addr) { + dev_err(&pdev->dev, "ioremap failed\n"); + err = -ENOMEM; + goto probe_exit_iounmap; + } + + priv->pru_arm_iomap.syscfg_io_addr = IO_ADDRESS(DA8XX_SYSCFG0_BASE); + if (!priv->pru_arm_iomap.syscfg_io_addr) { + dev_err(&pdev->dev, "ioremap failed\n"); + err = -ENOMEM; + goto probe_exit_iounmap; + } + + priv->ndev = ndev; + priv->trx_irq = trx_irq->start; + + priv->can.bittiming_const = NULL; + priv->can.do_set_bittiming = omapl_pru_can_set_bittiming; + priv->can.do_set_mode = omapl_pru_can_set_mode; + priv->can.do_get_state = omapl_pru_can_get_state; + priv->can_tx_hndl.u8prunumber = CAN_TX_PRU_1; + priv->can_rx_hndl.u8prunumber = CAN_RX_PRU_0; + + ndev->flags |= (IFF_ECHO | IFF_NOARP); /* we support local echo, no arp */ + platform_set_drvdata(pdev, ndev); + SET_NETDEV_DEV(ndev, &pdev->dev); + ndev->netdev_ops = &omapl_pru_can_netdev_ops; + + priv->clk = clk_get(&pdev->dev, "pru_ck"); + if (IS_ERR(priv->clk)) { + dev_err(&pdev->dev, "no clock available\n"); + err = PTR_ERR(priv->clk); + priv->clk = NULL; + goto probe_exit_candev; + } + clk_enable(priv->clk); + priv->can.clock.freq = clk_get_rate(priv->clk); + + priv->clk_timer = clk_get(&pdev->dev, "pll1_sysclk2"); + if (IS_ERR(priv->clk_timer)) { + dev_err(&pdev->dev, "no timer clock available\n"); + err = PTR_ERR(priv->clk_timer); + priv->clk_timer = NULL; + goto probe_exit_candev; + } + priv->timer_freq = clk_get_rate(priv->clk_timer); + + err = register_candev(ndev); + if (err) { + dev_err(&pdev->dev, "register_candev() failed\n"); + err = -ENODEV; + goto probe_exit_clk; + } + + err = request_firmware(&priv->fw_tx, "PRU_CAN_Emulation_Tx.bin", + &pdev->dev); + if (err) { + dev_err(&pdev->dev, "can't load firmware\n"); + err = -ENODEV; + goto probe_exit_clk; + } + + dev_info(&pdev->dev, "fw_tx size %d. downloading...\n", + priv->fw_tx->size); + + err = request_firmware(&priv->fw_rx, "PRU_CAN_Emulation_Rx.bin", + &pdev->dev); + if (err) { + dev_err(&pdev->dev, "can't load firmware\n"); + err = -ENODEV; + goto probe_release_fw; + } + dev_info(&pdev->dev, "fw_rx size %d. downloading...\n", + priv->fw_rx->size); + + fw_pru.ptr_pru1 = kmalloc(priv->fw_tx->size, GFP_KERNEL); + memcpy((void *)fw_pru.ptr_pru1, (const void *)priv->fw_tx->data, + priv->fw_tx->size); + fw_pru.u32_pru1_code_size = priv->fw_tx->size; + fw_pru.ptr_pru0 = kmalloc(priv->fw_rx->size, GFP_KERNEL); + memcpy((void *)fw_pru.ptr_pru0, (const void *)priv->fw_rx->data, + priv->fw_rx->size); + fw_pru.u32_pru0_code_size = priv->fw_rx->size; + + /* init the pru */ + pru_can_emulation_init(&priv->pru_arm_iomap, priv->can.clock.freq); + + while ((pru_can_check_init_status()) && (retries++ < MAX_INIT_RETRIES)) + udelay(retries); + + if (MAX_INIT_RETRIES <= retries) { + dev_err(&pdev->dev, "failed to initialize the pru\n"); + err = -ENODEV; + goto probe_release_fw_1; + } + + pru_can_enable(); + /* download firmware into pru */ + err = pru_can_download_firmware(&fw_pru, 0); + if (err) { + dev_err(&pdev->dev, "firmware download error\n"); + err = -ENODEV; + goto probe_release_fw_1; + } + err = pru_can_download_firmware(&fw_pru, 1); + if (err) { + dev_err(&pdev->dev, "firmware download error\n"); + err = -ENODEV; + goto probe_release_fw_1; + } + + if (pru_can_calculatetiming(DFLT_PRU_FREQ, DFLT_PRU_BITRATE) != 0) + return -EINVAL; + pru_can_run(0); + pru_can_run(1); + kfree((const void *)fw_pru.ptr_pru0); + kfree((const void *)fw_pru.ptr_pru1); + + /*Create The Work Queue */ + priv->pru_can_wQ = create_freezeable_workqueue("omapl_pru_wQ"); + if (priv->pru_can_wQ == NULL) + dev_err(&pdev->dev, "failed to create work queue\n"); + + INIT_WORK(&priv->rx_work, omapl_pru_can_rx_wQ); + dev_info(&pdev->dev, + "%s device registered" + "(&reg_base=0x%p, trx_irq = %d, clk = %d)\n", + DRV_NAME, priv->pru_arm_iomap.pru_io_addr, priv->trx_irq, + priv->can.clock.freq); + return 0; + +probe_release_fw_1: + kfree((const void *)fw_pru.ptr_pru0); + kfree((const void *)fw_pru.ptr_pru1); + release_firmware(priv->fw_rx); +probe_release_fw: + release_firmware(priv->fw_tx); +probe_exit_clk: + clk_put(priv->clk); +probe_exit_candev: + if (NULL != ndev) + free_candev(ndev); +probe_exit_iounmap: + iounmap(priv->pru_arm_iomap.pru_io_addr); +probe_exit_free_region: + release_mem_region(res_mem->start, resource_size(res_mem)); +probe_exit: + return err; +} + +static int __devexit omapl_pru_can_remove(struct platform_device *pdev) +{ + struct resource *res; + struct net_device *ndev = platform_get_drvdata(pdev); + struct omapl_pru_can_priv *priv = netdev_priv(ndev); + + omapl_pru_can_stop(ndev); + + pru_can_emulation_exit(); + release_firmware(priv->fw_tx); + release_firmware(priv->fw_rx); + clk_put(priv->clk); + flush_workqueue(priv->pru_can_wQ); + destroy_workqueue(priv->pru_can_wQ); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + iounmap(priv->pru_arm_iomap.pru_io_addr); + release_mem_region(res->start, resource_size(res)); + unregister_candev(ndev); + free_candev(ndev); + platform_set_drvdata(pdev, NULL); + return 0; +} + +#ifdef CONFIG_PM +static int omapl_pru_can_suspend(struct platform_device *pdev, + pm_message_t mesg) +{ + dev_info(&pdev->dev, "%s not yet implemented\n", __func__); + return 0; +} + +static int omapl_pru_can_resume(struct platform_device *pdev) +{ + dev_info(&pdev->dev, "%s not yet implemented\n", __func__); + return 0; +} +#else +#define omapl_pru_can_suspend NULL +#define omapl_pru_can_resume NULL +#endif /* CONFIG_PM */ + +static struct platform_driver omapl_pru_can_driver = { + .probe = omapl_pru_can_probe, + .remove = __devexit_p(omapl_pru_can_remove), + .suspend = omapl_pru_can_suspend, + .resume = omapl_pru_can_resume, + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init omapl_pru_can_init(void) +{ + __can_debug(KERN_INFO DRV_DESC "\n"); + return platform_driver_register(&omapl_pru_can_driver); +} + +module_init(omapl_pru_can_init); + +static void __exit omapl_pru_can_exit(void) +{ + __can_debug(KERN_INFO DRV_DESC " unloaded\n"); + platform_driver_unregister(&omapl_pru_can_driver); +} + +module_exit(omapl_pru_can_exit); + +MODULE_AUTHOR("Subhasish Ghosh <subhasish@mistralsolutions.com>"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("omapl pru emulated CAN netdevice driver");

[RFC:,4/5] da850: SocketCAN compliant driver for TI's PRU CAN Lite Emulation.

Commit Message

Patch