| Message ID | 1310554333-25242-1-git-send-email-prakash.pm@ti.com (mailing list archive) |
|---|---|
| State | Awaiting Upstream |
| Headers | show |
Hello. On 13-07-2011 14:52, Manjunathappa, Prakash wrote: > Revised LCD controller in upcoming TI SoC which is an updated version of > LCDC IP that was found on TI's DA850 SoC supports 2048*2048 resolution. > Below are the encoding details: > Width: > Pixels Per Line = {pplmsb, ppllsb, 4'b1111} + 1 > Where pplmsb:1bit==>Raster Timing0[3], ppllsb:6bits==>Raster Timing0[9:4]. > And encoded value can range from 16 to 2048 in multiples of 16. > Height: > Lines Per Panel = {lpp_b10, lpp} > Where lpp:10bits==>Raster Timing1[9:0], lpp_b10:1bit==>Raster Timing2[26]. > And encoded value can range from 1 to 2048, programmable range is 0 to > 2047. > Patch is verified on emulation platform of upcoming SoC for updated > feature and on DA850 platform to make sure nothing existing breaks. > Signed-off-by: Manjunathappa, Prakash<prakash.pm@ti.com> > --- > Since v1: > 1)Fixed the bug in configuration of lpp_b10 in Raster Timing2[26] register. > 2)Reframed commit message. > drivers/video/da8xx-fb.c | 31 ++++++++++++++++++++++++++++--- > 1 files changed, 28 insertions(+), 3 deletions(-) > diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c > index 620f1c3..19ce407 100644 > --- a/drivers/video/da8xx-fb.c > +++ b/drivers/video/da8xx-fb.c > @@ -460,18 +460,43 @@ static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height, > > /* Set the Panel Width */ > /* Pixels per line = (PPL + 1)*16 */ > - /*0x3F in bits 4..9 gives max horisontal resolution = 1024 pixels*/ > - width&= 0x3f0; > + if (lcd_revision == LCD_VERSION_1) { > + /* > + * 0x3F in bits 4..9 gives max horizontal resolution = 1024 > + * pixels. > + */ > + width&= 0x3f0; > + } else { > + /* > + * 0x7F in bits 3..9 gives max horizontal resolution = 2048 Maybe bits 4..10? > + * pixels. > + */ > + width&= 0x7f0; > + } > + > reg = lcdc_read(LCD_RASTER_TIMING_0_REG); > reg &= 0xfffffc00; > - reg |= ((width >> 4) - 1) << 4; > + if (lcd_revision == LCD_VERSION_1) { > + reg |= ((width>> 4) - 1)<< 4; > + } else { > + width = ((width>> 4) - 1); Most outer parens not needed. > + reg |= ((width & 0x3f) << 4) | ((width& 0x40) >> 3); > + } > lcdc_write(reg, LCD_RASTER_TIMING_0_REG); > > /* Set the Panel Height */ > + /* Set bits 9:0 of Lines Per Pixel */ > reg = lcdc_read(LCD_RASTER_TIMING_1_REG); > reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00); > lcdc_write(reg, LCD_RASTER_TIMING_1_REG); > > + /* Set bit 10 of Lines Per Pixel */ > + if (lcd_revision == LCD_VERSION_2) { > + reg = lcdc_read(LCD_RASTER_TIMING_2_REG); > + reg |= (((height - 1) & 0x400) << 16); Most outer parens not needed. WBR, Sergei
Hi Sergei, On Thu, Jul 14, 2011 at 16:05:35, Sergei Shtylyov wrote: > Hello. > > On 13-07-2011 14:52, Manjunathappa, Prakash wrote: > > > Revised LCD controller in upcoming TI SoC which is an updated version of > > LCDC IP that was found on TI's DA850 SoC supports 2048*2048 resolution. > > Below are the encoding details: > > Width: > > Pixels Per Line = {pplmsb, ppllsb, 4'b1111} + 1 > > Where pplmsb:1bit==>Raster Timing0[3], ppllsb:6bits==>Raster Timing0[9:4]. > > And encoded value can range from 16 to 2048 in multiples of 16. > > > Height: > > Lines Per Panel = {lpp_b10, lpp} > > Where lpp:10bits==>Raster Timing1[9:0], lpp_b10:1bit==>Raster Timing2[26]. > > And encoded value can range from 1 to 2048, programmable range is 0 to > > 2047. > > > Patch is verified on emulation platform of upcoming SoC for updated > > feature and on DA850 platform to make sure nothing existing breaks. > > > Signed-off-by: Manjunathappa, Prakash<prakash.pm@ti.com> > > --- > > Since v1: > > 1)Fixed the bug in configuration of lpp_b10 in Raster Timing2[26] register. > > 2)Reframed commit message. > > drivers/video/da8xx-fb.c | 31 ++++++++++++++++++++++++++++--- > > 1 files changed, 28 insertions(+), 3 deletions(-) > > > diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c > > index 620f1c3..19ce407 100644 > > --- a/drivers/video/da8xx-fb.c > > +++ b/drivers/video/da8xx-fb.c > > @@ -460,18 +460,43 @@ static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height, > > > > /* Set the Panel Width */ > > /* Pixels per line = (PPL + 1)*16 */ > > - /*0x3F in bits 4..9 gives max horisontal resolution = 1024 pixels*/ > > - width&= 0x3f0; > > + if (lcd_revision == LCD_VERSION_1) { > > + /* > > + * 0x3F in bits 4..9 gives max horizontal resolution = 1024 > > + * pixels. > > + */ > > + width&= 0x3f0; > > + } else { > > + /* > > + * 0x7F in bits 3..9 gives max horizontal resolution = 2048 > > Maybe bits 4..10? Correct, I will fix this comment. > > > + * pixels. > > + */ > > + width&= 0x7f0; > > + } > > + > > reg = lcdc_read(LCD_RASTER_TIMING_0_REG); > > reg &= 0xfffffc00; > > - reg |= ((width >> 4) - 1) << 4; > > + if (lcd_revision == LCD_VERSION_1) { > > + reg |= ((width>> 4) - 1)<< 4; > > + } else { > > + width = ((width>> 4) - 1); > > Most outer parens not needed. Ok. I will remove them. > > > + reg |= ((width & 0x3f) << 4) | ((width& 0x40) >> 3); > > + } > > lcdc_write(reg, LCD_RASTER_TIMING_0_REG); > > > > /* Set the Panel Height */ > > + /* Set bits 9:0 of Lines Per Pixel */ > > reg = lcdc_read(LCD_RASTER_TIMING_1_REG); > > reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00); > > lcdc_write(reg, LCD_RASTER_TIMING_1_REG); > > > > + /* Set bit 10 of Lines Per Pixel */ > > + if (lcd_revision == LCD_VERSION_2) { > > + reg = lcdc_read(LCD_RASTER_TIMING_2_REG); > > + reg |= (((height - 1) & 0x400) << 16); > > Most outer parens not needed. Ok. I will remove them. Thanks, Prakash > > WBR, Sergei >
Hello, Bashing my head against the wall trying to get the VPFE drivers to send up both fields of D1 interlaced video so I can use the DEI algorithm for deinterlacing instead of the poor-man's method of just throwing a field away. Anyone have any clues as how to modify the driver to make this happen in chained mode? I was hoping that just preserving the vertical resolution in ipipe_set_input_win (and ipipe_get_input_win) would work, but that just makes my system hang. There have been allusions in other threads about the need to modify some ISR's to make this work. Anyone trod down this path? Thanks, Paul
Paul, If you wan to capture D1 interlaced video from VPFE, why you wan to connect previewer and reszier in chained mode with CCDC? Simple way will be to capture from CCDC. You need to change ISR routines though. For example, If you are using arago source(http://arago-project.org/git/projects/?p=linux-davinci.git;a=shortlog;h=refs/heads/r37), you can change vpfe_isr() and vpfe_vdint1_isr() to capture interlaced video frames. In addition to above changes, you need to change programming of CCDC's SDOFST register in CCDC driver module [ Refer to section 6.1.15 of VPFE user guide]. Regards, Nag
Nag,
Thanks for getting in touch with me, really appreciate it.
I'm missing the big picture here. What, in broad strokes, do I need to change about the ISR routine to make this work? Just need the general concept, 'cause I'm missing it.
My understanding is that the two fields are stored interleaved in memory. Where is the magic, in chained mode, that makes the resizer skip every other line?
In previous experiments, I modified SDOFST to not skip lines, but it still looked like "normal" video. Does this register change behavior in chained mode, or only in one shot when we pull from SDRAM?
Thanks!
Paul
-----Original Message-----
From: Netagunte, Nagabhushana [mailto:nagabhushana.netagunte@ti.com]
Sent: Tuesday, July 19, 2011 7:03 AM
To: Paul Stuart; davinci-linux-open-source@linux.davincidsp.com
Subject: RE: DM365: How to disable deinterlacing in Chained Resizer mode
Paul,
If you wan to capture D1 interlaced video from VPFE, why you wan to connect previewer and reszier in chained mode with CCDC?
Simple way will be to capture from CCDC. You need to change ISR routines though.
For example, If you are using arago source(http://arago-project.org/git/projects/?p=linux-davinci.git;a=shortlog;h=refs/heads/r37),
you can change vpfe_isr() and vpfe_vdint1_isr() to capture interlaced video frames.
In addition to above changes, you need to change programming of CCDC's SDOFST register in CCDC driver module [ Refer to section 6.1.15 of VPFE user guide].
Regards,
Nag
Paul, Lets continue this discussion on e2e forum as I see lot of questions on forum . http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/100/p/123233/439517.aspx#439517 Regards, Nag
diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c index 620f1c3..19ce407 100644 --- a/drivers/video/da8xx-fb.c +++ b/drivers/video/da8xx-fb.c @@ -460,18 +460,43 @@ static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height, /* Set the Panel Width */ /* Pixels per line = (PPL + 1)*16 */ - /*0x3F in bits 4..9 gives max horisontal resolution = 1024 pixels*/ - width &= 0x3f0; + if (lcd_revision == LCD_VERSION_1) { + /* + * 0x3F in bits 4..9 gives max horizontal resolution = 1024 + * pixels. + */ + width &= 0x3f0; + } else { + /* + * 0x7F in bits 3..9 gives max horizontal resolution = 2048 + * pixels. + */ + width &= 0x7f0; + } + reg = lcdc_read(LCD_RASTER_TIMING_0_REG); reg &= 0xfffffc00; - reg |= ((width >> 4) - 1) << 4; + if (lcd_revision == LCD_VERSION_1) { + reg |= ((width >> 4) - 1) << 4; + } else { + width = ((width >> 4) - 1); + reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3); + } lcdc_write(reg, LCD_RASTER_TIMING_0_REG); /* Set the Panel Height */ + /* Set bits 9:0 of Lines Per Pixel */ reg = lcdc_read(LCD_RASTER_TIMING_1_REG); reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00); lcdc_write(reg, LCD_RASTER_TIMING_1_REG); + /* Set bit 10 of Lines Per Pixel */ + if (lcd_revision == LCD_VERSION_2) { + reg = lcdc_read(LCD_RASTER_TIMING_2_REG); + reg |= (((height - 1) & 0x400) << 16); + lcdc_write(reg, LCD_RASTER_TIMING_2_REG); + } + /* Set the Raster Order of the Frame Buffer */ reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8); if (raster_order)
Revised LCD controller in upcoming TI SoC which is an updated version of LCDC IP that was found on TI's DA850 SoC supports 2048*2048 resolution. Below are the encoding details: Width: Pixels Per Line = {pplmsb, ppllsb, 4'b1111} + 1 Where pplmsb:1bit==>Raster Timing0[3], ppllsb:6bits==>Raster Timing0[9:4]. And encoded value can range from 16 to 2048 in multiples of 16. Height: Lines Per Panel = {lpp_b10, lpp} Where lpp:10bits==>Raster Timing1[9:0], lpp_b10:1bit==>Raster Timing2[26]. And encoded value can range from 1 to 2048, programmable range is 0 to 2047. Patch is verified on emulation platform of upcoming SoC for updated feature and on DA850 platform to make sure nothing existing breaks. Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> --- Since v1: 1)Fixed the bug in configuration of lpp_b10 in Raster Timing2[26] register. 2)Reframed commit message. drivers/video/da8xx-fb.c | 31 ++++++++++++++++++++++++++++--- 1 files changed, 28 insertions(+), 3 deletions(-)