From patchwork Wed Jul 18 15:21:11 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Manjunathappa, Prakash" X-Patchwork-Id: 1211791 Return-Path: X-Original-To: patchwork-davinci@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from comal.ext.ti.com (comal.ext.ti.com [198.47.26.152]) by patchwork1.kernel.org (Postfix) with ESMTP id 427B63FD4F for ; Wed, 18 Jul 2012 15:38:03 +0000 (UTC) Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id q6IFZxJE028723; Wed, 18 Jul 2012 10:35:59 -0500 Received: from DFLE71.ent.ti.com (dfle71.ent.ti.com [128.247.5.62]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id q6IFZxr6016367; Wed, 18 Jul 2012 10:35:59 -0500 Received: from dlelxv24.itg.ti.com (172.17.1.199) by dfle71.ent.ti.com (128.247.5.62) with Microsoft SMTP Server id 14.1.323.3; Wed, 18 Jul 2012 10:35:59 -0500 Received: from linux.omap.com (dlelxs01.itg.ti.com [157.170.227.31]) by dlelxv24.itg.ti.com (8.13.8/8.13.8) with ESMTP id q6IFZwYC023035; Wed, 18 Jul 2012 10:35:59 -0500 Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id D628380627; Wed, 18 Jul 2012 10:35:58 -0500 (CDT) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dbdp20.itg.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by linux.omap.com (Postfix) with ESMTP id D4C4C80626 for ; Wed, 18 Jul 2012 10:35:56 -0500 (CDT) Received: from DBDE71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id q6IFZsWe023851; Wed, 18 Jul 2012 21:05:54 +0530 (IST) Received: from dbdp32.itg.ti.com (172.24.170.251) by DBDE71.ent.ti.com (172.24.170.149) with Microsoft SMTP Server id 14.1.323.3; Wed, 18 Jul 2012 21:05:53 +0530 Received: from ucmsshproxy.india.ext.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by dbdp32.itg.ti.com (8.13.8/8.13.8) with SMTP id q6IFZp9u019558; Wed, 18 Jul 2012 21:05:52 +0530 Received: from symphony.india.ext.ti.com (unknown [192.168.247.13]) by ucmsshproxy.india.ext.ti.com (Postfix) with ESMTP id A2DDA158002; Wed, 18 Jul 2012 21:05:51 +0530 (IST) Received: from linux-psp-server.india.ext.ti.com (linux-psp-server [192.168.247.76]) by symphony.india.ext.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id q6IFZoI01452; Wed, 18 Jul 2012 21:05:50 +0530 (IST) From: "Manjunathappa, Prakash" To: Subject: [PATCH RESEND] video: da8xx-fb rev2: fix disabling of palette completion interrupt Date: Wed, 18 Jul 2012 20:51:11 +0530 Message-ID: <1342624871-5947-1-git-send-email-prakash.pm@ti.com> X-Mailer: git-send-email 1.7.1 MIME-Version: 1.0 CC: , Florian Tobias Schandinat X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: Errors-To: davinci-linux-open-source-bounces@linux.davincidsp.com Writing '1' to particular bit of IRQENABLE_CLEAR register disables the corresponding interrupt on revision 2 LCDC. This register was wrongly configured to disable all previous enabled interrupts instead of disabling only palette completion interrupt. Patch fixes it by clearing only palette completion interrupt bit. Signed-off-by: Manjunathappa, Prakash --- Resending as my earlier patch seems like not reached fbdev mailing list. drivers/video/da8xx-fb.c | 7 ++----- 1 files changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c index 47118c7..88e98ea 100644 --- a/drivers/video/da8xx-fb.c +++ b/drivers/video/da8xx-fb.c @@ -715,7 +715,6 @@ static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg) { struct da8xx_fb_par *par = arg; u32 stat = lcdc_read(LCD_MASKED_STAT_REG); - u32 reg_int; if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) { lcd_disable_raster(); @@ -732,10 +731,8 @@ static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg) lcdc_write(stat, LCD_MASKED_STAT_REG); - /* Disable PL completion inerrupt */ - reg_int = lcdc_read(LCD_INT_ENABLE_CLR_REG) | - (LCD_V2_PL_INT_ENA); - lcdc_write(reg_int, LCD_INT_ENABLE_CLR_REG); + /* Disable PL completion interrupt */ + lcdc_write(LCD_V2_PL_INT_ENA, LCD_INT_ENABLE_CLR_REG); /* Setup and start data loading mode */ lcd_blit(LOAD_DATA, par);