| Message ID | 1349246100-7477-1-git-send-email-prabhakar.lad@ti.com (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
On 10/3/2012 12:05 PM, Prabhakar wrote: > From: Lad, Prabhakar <prabhakar.lad@ti.com> > > while testing display on dm644x, for ED out-range signals > was observed. This patch fixes appropriate clock setting > for ED. Can you please clarify what you mean by "out range signal"? Are there any user visible artifacts on the display? What was the clock being provided earlier and what is the value after this patch? Also, is the issue severe enough that this patch should be applied to stable tree as well? Thanks, Sekhar
Hi Sekhar, On Wed, Oct 3, 2012 at 4:08 PM, Sekhar Nori <nsekhar@ti.com> wrote: > On 10/3/2012 12:05 PM, Prabhakar wrote: >> From: Lad, Prabhakar <prabhakar.lad@ti.com> >> >> while testing display on dm644x, for ED out-range signals >> was observed. This patch fixes appropriate clock setting >> for ED. > > Can you please clarify what you mean by "out range signal"? Are there > any user visible artifacts on the display? What was the clock being > provided earlier and what is the value after this patch? > > Also, is the issue severe enough that this patch should be applied to > stable tree as well? > Ideally a clock of 54Mhz is required for enhanced definition to work, which it was actually set to but while testing I noticed out-of-range signal. The out-of-range signal is often caused when the field rate is above the rate that the television will handle. When this is the case the TV or monitor displays "Out-Of-Range Signal". Reducing the clock fixed it. now the clock is set to 27Mhz. Regards, --Prabhakar > Thanks, > Sekhar
On 10/4/2012 10:22 AM, Prabhakar Lad wrote: > Hi Sekhar, > > On Wed, Oct 3, 2012 at 4:08 PM, Sekhar Nori <nsekhar@ti.com> wrote: >> On 10/3/2012 12:05 PM, Prabhakar wrote: >>> From: Lad, Prabhakar <prabhakar.lad@ti.com> >>> >>> while testing display on dm644x, for ED out-range signals >>> was observed. This patch fixes appropriate clock setting >>> for ED. >> >> Can you please clarify what you mean by "out range signal"? Are there >> any user visible artifacts on the display? What was the clock being >> provided earlier and what is the value after this patch? >> >> Also, is the issue severe enough that this patch should be applied to >> stable tree as well? >> > Ideally a clock of 54Mhz is required for enhanced definition to > work, which it was actually set to but while testing I noticed > out-of-range signal. The out-of-range signal is often caused > when the field rate is above the rate that the television will handle. > When this is the case the TV or monitor displays "Out-Of-Range Signal". > > Reducing the clock fixed it. now the clock is set to 27Mhz. So, is the requirement for ED 54MHz or lower? Still trying to explain myself how 27MHz is working where a 54MHz is required. I guess there is also a lower limit on what the frequency should be? Sorry I am not familiar will all the video concepts, hence the questions. Thanks, Sekhar
Sekhar On Thu, Oct 4, 2012 at 12:43 PM, Sekhar Nori <nsekhar@ti.com> wrote: > On 10/4/2012 10:22 AM, Prabhakar Lad wrote: >> Hi Sekhar, >> >> On Wed, Oct 3, 2012 at 4:08 PM, Sekhar Nori <nsekhar@ti.com> wrote: >>> On 10/3/2012 12:05 PM, Prabhakar wrote: >>>> From: Lad, Prabhakar <prabhakar.lad@ti.com> >>>> >>>> while testing display on dm644x, for ED out-range signals >>>> was observed. This patch fixes appropriate clock setting >>>> for ED. >>> >>> Can you please clarify what you mean by "out range signal"? Are there >>> any user visible artifacts on the display? What was the clock being >>> provided earlier and what is the value after this patch? >>> >>> Also, is the issue severe enough that this patch should be applied to >>> stable tree as well? >>> >> Ideally a clock of 54Mhz is required for enhanced definition to >> work, which it was actually set to but while testing I noticed >> out-of-range signal. The out-of-range signal is often caused >> when the field rate is above the rate that the television will handle. >> When this is the case the TV or monitor displays "Out-Of-Range Signal". >> >> Reducing the clock fixed it. now the clock is set to 27Mhz. > > So, is the requirement for ED 54MHz or lower? Still trying to explain > myself how 27MHz is working where a 54MHz is required. I guess there is > also a lower limit on what the frequency should be? > Ideally its 54Mhz, but I see in the datasheet for AD7342/3 [1] it can also work at 27Mhz too. Regards, --Prabhakar [1] http://www.analog.com/static/imported-files/data_sheets/ADV7342_7343.pdf > Sorry I am not familiar will all the video concepts, hence the questions. > > Thanks, > Sekhar
On 10/4/2012 7:23 PM, Prabhakar Lad wrote: > Sekhar > > On Thu, Oct 4, 2012 at 12:43 PM, Sekhar Nori <nsekhar@ti.com> wrote: >> On 10/4/2012 10:22 AM, Prabhakar Lad wrote: >>> Hi Sekhar, >>> >>> On Wed, Oct 3, 2012 at 4:08 PM, Sekhar Nori <nsekhar@ti.com> wrote: >>>> On 10/3/2012 12:05 PM, Prabhakar wrote: >>>>> From: Lad, Prabhakar <prabhakar.lad@ti.com> >>>>> >>>>> while testing display on dm644x, for ED out-range signals >>>>> was observed. This patch fixes appropriate clock setting >>>>> for ED. >>>> >>>> Can you please clarify what you mean by "out range signal"? Are there >>>> any user visible artifacts on the display? What was the clock being >>>> provided earlier and what is the value after this patch? >>>> >>>> Also, is the issue severe enough that this patch should be applied to >>>> stable tree as well? >>>> >>> Ideally a clock of 54Mhz is required for enhanced definition to >>> work, which it was actually set to but while testing I noticed >>> out-of-range signal. The out-of-range signal is often caused >>> when the field rate is above the rate that the television will handle. >>> When this is the case the TV or monitor displays "Out-Of-Range Signal". >>> >>> Reducing the clock fixed it. now the clock is set to 27Mhz. >> >> So, is the requirement for ED 54MHz or lower? Still trying to explain >> myself how 27MHz is working where a 54MHz is required. I guess there is >> also a lower limit on what the frequency should be? >> > Ideally its 54Mhz, but I see in the datasheet for AD7342/3 [1] it can also > work at 27Mhz too. So, based on this discussion I think a better description would be: " Fix the video clock setting when custom timings are used with pclock <= 27MHz. Existing clock selection uses PLL2 mode which results in a 54MHz clock where as using the MXI mode results in a 27MHz clock (which is the one actually desired). This affects the Enhanced Definition (ED) support on DM644x. Without this patch, out-range signals errors are were observed on the TV. An out-of-range signal is often caused when the field rate is above the rate that the television will handle. " Is this accurate? In future, please try to be descriptive in patch description as it will help understand what the patch is doing and why (which in turn will lead to the patch getting accepted faster). Also I assume you need this patch in v3.7? Or can I send it for v3.8? Thanks, Sekhar
Sekhar, On Fri, Oct 26, 2012 at 1:05 PM, Sekhar Nori <nsekhar@ti.com> wrote: > On 10/4/2012 7:23 PM, Prabhakar Lad wrote: >> Sekhar >> >> On Thu, Oct 4, 2012 at 12:43 PM, Sekhar Nori <nsekhar@ti.com> wrote: >>> On 10/4/2012 10:22 AM, Prabhakar Lad wrote: >>>> Hi Sekhar, >>>> >>>> On Wed, Oct 3, 2012 at 4:08 PM, Sekhar Nori <nsekhar@ti.com> wrote: >>>>> On 10/3/2012 12:05 PM, Prabhakar wrote: >>>>>> From: Lad, Prabhakar <prabhakar.lad@ti.com> >>>>>> >>>>>> while testing display on dm644x, for ED out-range signals >>>>>> was observed. This patch fixes appropriate clock setting >>>>>> for ED. >>>>> >>>>> Can you please clarify what you mean by "out range signal"? Are there >>>>> any user visible artifacts on the display? What was the clock being >>>>> provided earlier and what is the value after this patch? >>>>> >>>>> Also, is the issue severe enough that this patch should be applied to >>>>> stable tree as well? >>>>> >>>> Ideally a clock of 54Mhz is required for enhanced definition to >>>> work, which it was actually set to but while testing I noticed >>>> out-of-range signal. The out-of-range signal is often caused >>>> when the field rate is above the rate that the television will handle. >>>> When this is the case the TV or monitor displays "Out-Of-Range Signal". >>>> >>>> Reducing the clock fixed it. now the clock is set to 27Mhz. >>> >>> So, is the requirement for ED 54MHz or lower? Still trying to explain >>> myself how 27MHz is working where a 54MHz is required. I guess there is >>> also a lower limit on what the frequency should be? >>> >> Ideally its 54Mhz, but I see in the datasheet for AD7342/3 [1] it can also >> work at 27Mhz too. > > So, based on this discussion I think a better description would be: > > " > Fix the video clock setting when custom timings are used with pclock <= > 27MHz. Existing clock selection uses PLL2 mode which results in a 54MHz > clock where as using the MXI mode results in a 27MHz clock (which is the > one actually desired). > > This affects the Enhanced Definition (ED) support on DM644x. Without > this patch, out-range signals errors are were observed on the TV. An > out-of-range signal is often caused when the field rate is above the > rate that the television will handle. > " > > Is this accurate? In future, please try to be descriptive in patch > description as it will help understand what the patch is doing and why > (which in turn will lead to the patch getting accepted faster). > Looks good. I'll make sure to have descriptive commit message hence forth. > Also I assume you need this patch in v3.7? Or can I send it for v3.8? > Since its a fix it would be good if its queued for v3.7. Regards, --Prabhakar > Thanks, > Sekhar
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index 79d2880..688484b 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -713,8 +713,7 @@ static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type, break; case VPBE_ENC_CUSTOM_TIMINGS: if (pclock <= 27000000) { - v |= DM644X_VPSS_MUXSEL_PLL2_MODE | - DM644X_VPSS_DACCLKEN; + v |= DM644X_VPSS_DACCLKEN; writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL)); } else { /*