From patchwork Thu Mar 14 10:37:32 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: avinash philip X-Patchwork-Id: 2269091 Return-Path: X-Original-To: patchwork-davinci@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from devils.ext.ti.com (devils.ext.ti.com [198.47.26.153]) by patchwork1.kernel.org (Postfix) with ESMTP id E25873FC8A for ; Thu, 14 Mar 2013 10:37:35 +0000 (UTC) Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id r2EAbZvi002567 for ; Thu, 14 Mar 2013 05:37:35 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id r2EAbZAl011294 for ; Thu, 14 Mar 2013 05:37:35 -0500 Received: from dlelxv23.itg.ti.com (172.17.1.198) by dfle73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.1.323.3; Thu, 14 Mar 2013 05:37:35 -0500 Received: from linux.omap.com (dlelxs01.itg.ti.com [157.170.227.31]) by dlelxv23.itg.ti.com (8.13.8/8.13.8) with ESMTP id r2EAbZZ8004445 for ; Thu, 14 Mar 2013 05:37:35 -0500 Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id 1C99E80628 for ; Thu, 14 Mar 2013 04:37:35 -0600 (CST) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dbdp20.itg.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by linux.omap.com (Postfix) with ESMTP id EAF0880626 for ; Thu, 14 Mar 2013 04:37:22 -0600 (CST) Received: from DBDE70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id r2EAbLdX018843; Thu, 14 Mar 2013 16:07:21 +0530 (IST) Received: from dbdp32.itg.ti.com (172.24.170.251) by dbde70.ent.ti.com (172.24.170.148) with Microsoft SMTP Server id 14.1.323.3; Thu, 14 Mar 2013 16:07:21 +0530 Received: from ucmsshproxy.india.ext.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by dbdp32.itg.ti.com (8.13.8/8.13.8) with SMTP id r2EAbJqG004228; Thu, 14 Mar 2013 16:07:19 +0530 Received: from symphony.india.ext.ti.com (unknown [192.168.247.13]) by ucmsshproxy.india.ext.ti.com (Postfix) with ESMTP id A1C75158002; Thu, 14 Mar 2013 16:07:19 +0530 (IST) Received: from ubuntu-psp-linux.india.ext.ti.com (ubuntu-psp-linux [192.168.247.46]) by symphony.india.ext.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id r2EAbJR11612; Thu, 14 Mar 2013 16:07:19 +0530 (IST) From: Philip Avinash To: , Subject: [PATCH 2/3] ARM: davinci: da850: Enable EHRPWM TBCLK from CFG_CHIP1 Date: Thu, 14 Mar 2013 16:07:32 +0530 Message-ID: <1363257453-24747-3-git-send-email-avinashphilip@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1363257453-24747-1-git-send-email-avinashphilip@ti.com> References: <1363257453-24747-1-git-send-email-avinashphilip@ti.com> MIME-Version: 1.0 CC: , Philip Avinash , , X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: Errors-To: davinci-linux-open-source-bounces+patchwork-davinci=patchwork.kernel.org@linux.davincidsp.com da850 platforms require TBCLK synchronization in CFG_CHIP1 register for TBCLK enable in EHRPWM modules. Enabling of TBCLK is done only if EHRPWM DT node status is set to "okay" DT blob. Also adds macro definitions for DA8XX_EHRPWM_TBCLKSYNC and DA8XX_CFGCHIP1_REG. Signed-off-by: Philip Avinash --- :100644 100644 6b7a0a2... 72466ab... M arch/arm/mach-davinci/da8xx-dt.c :100644 100644 de439b7... be77ce2... M arch/arm/mach-davinci/include/mach/da8xx.h arch/arm/mach-davinci/da8xx-dt.c | 15 +++++++++++++++ arch/arm/mach-davinci/include/mach/da8xx.h | 1 + 2 files changed, 16 insertions(+) diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c index 6b7a0a2..72466ab 100644 --- a/arch/arm/mach-davinci/da8xx-dt.c +++ b/arch/arm/mach-davinci/da8xx-dt.c @@ -19,6 +19,7 @@ #include #define DA8XX_NUM_UARTS 3 +#define DA8XX_EHRPWM_TBCLKSYNC BIT(12) void __init da8xx_uart_clk_enable(void) { @@ -47,10 +48,24 @@ struct of_dev_auxdata da850_auxdata_lookup[] __initdata = { static void __init da850_init_machine(void) { + struct device_node *ehrpwm_np; + const char *ehrpwm_compat = "ti,da850-ehrpwm"; + void __iomem *cfg_chip1_base; + + cfg_chip1_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG); + of_platform_populate(NULL, of_default_bus_match_table, da850_auxdata_lookup, NULL); da8xx_uart_clk_enable(); + + for_each_compatible_node(ehrpwm_np, NULL, ehrpwm_compat) + if (of_device_is_available(ehrpwm_np)) { + /* Enable TBCLK synchronization for EHRWPM modules */ + writel(readl(cfg_chip1_base) | DA8XX_EHRPWM_TBCLKSYNC, + cfg_chip1_base); + break; + } } static const char *da850_boards_compat[] __initdata = { diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index de439b7..be77ce2 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -55,6 +55,7 @@ extern unsigned int da850_max_speed; #define DA8XX_SYSCFG0_VIRT(x) (da8xx_syscfg0_base + (x)) #define DA8XX_JTAG_ID_REG 0x18 #define DA8XX_CFGCHIP0_REG 0x17c +#define DA8XX_CFGCHIP1_REG 0x180 #define DA8XX_CFGCHIP2_REG 0x184 #define DA8XX_CFGCHIP3_REG 0x188