From patchwork Fri Mar 15 15:11:42 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 2278491 Return-Path: X-Original-To: patchwork-davinci@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from comal.ext.ti.com (comal.ext.ti.com [198.47.26.152]) by patchwork1.kernel.org (Postfix) with ESMTP id 100003FC8A for ; Fri, 15 Mar 2013 15:17:29 +0000 (UTC) Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id r2FFDRWB010120; Fri, 15 Mar 2013 10:13:27 -0500 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id r2FFDRTq029534; Fri, 15 Mar 2013 10:13:27 -0500 Received: from dlelxv24.itg.ti.com (172.17.1.199) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.2.342.3; Fri, 15 Mar 2013 10:13:27 -0500 Received: from linux.omap.com (dlelxs01.itg.ti.com [157.170.227.31]) by dlelxv24.itg.ti.com (8.13.8/8.13.8) with ESMTP id r2FFDROK014278; Fri, 15 Mar 2013 10:13:27 -0500 Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id ECF8C80627; Fri, 15 Mar 2013 09:13:26 -0600 (CST) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dflp53.itg.ti.com (dflp53.itg.ti.com [128.247.5.6]) by linux.omap.com (Postfix) with ESMTP id 8EFBD8062A for ; Fri, 15 Mar 2013 09:12:18 -0600 (CST) Received: from red.ext.ti.com (red.ext.ti.com [192.94.93.37]) by dflp53.itg.ti.com (8.13.8/8.13.8) with ESMTP id r2FFCIYx026567 for ; Fri, 15 Mar 2013 10:12:18 -0500 (CDT) Received: from mail6.bemta8.messagelabs.com (mail6.bemta8.messagelabs.com [216.82.243.55]) by red.ext.ti.com (8.13.7/8.13.7) with ESMTP id r2FFCH4V032671 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Fri, 15 Mar 2013 10:12:18 -0500 Received: from [216.82.242.147:32513] by server-9.bemta-8.messagelabs.com id 4E/28-32481-15A33415; Fri, 15 Mar 2013 15:12:17 +0000 X-Env-Sender: prabhakar.csengg@gmail.com X-Msg-Ref: server-2.tower-95.messagelabs.com!1363360325!28995461!1 X-Originating-IP: [209.85.160.52] X-SpamReason: No, hits=0.5 required=7.0 tests=BODY_RANDOM_LONG, ML_RADAR_SPEW_LINKS_14,spamassassin: X-StarScan-Received: X-StarScan-Version: 6.8.6.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 15762 invoked from network); 15 Mar 2013 15:12:06 -0000 Received: from mail-pb0-f52.google.com (HELO mail-pb0-f52.google.com) (209.85.160.52) by server-2.tower-95.messagelabs.com with RC4-SHA encrypted SMTP; 15 Mar 2013 15:12:06 -0000 Received: by mail-pb0-f52.google.com with SMTP id ma3so3957476pbc.39 for ; Fri, 15 Mar 2013 08:12:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=21oSPEqu2hUVdBvwJpOfVLnukQgYU0iExEeDaFxqYEY=; b=TGnnr2gJBt8q3e06/okg099ZSpQwvB2m/2GZ7ailS6a9kmEKSKHbvTEsailZwYxPc5 pnG7sfzcpqCXrZWLfkHIOUxXS62b2ieTkGZVAnKUoPQOu6IxyJ25YvECAmOyE65coyEG nzqYyJ8HRnfMPqRxaHvp3AhKQMuHGPxb+kOicp+9yxppai7kyYs0RsrpSytGvrmzGoLY JoWq0PCnr6O4xZ0rBiW7MsTMOAvCXbgBWTSyrKjN9Ugd+RgIXSllUUHsBAhczPObnMpm Zof2hIB3LePSnhhloqPyeFZKlGHom6vTHvsLQRDWFDco7CLqJ9buXmERpU7DFlSUCHem 50Gg== X-Received: by 10.68.76.1 with SMTP id g1mr17040910pbw.12.1363360324795; Fri, 15 Mar 2013 08:12:04 -0700 (PDT) Received: from localhost.localdomain ([59.98.241.67]) by mx.google.com with ESMTPS id kl4sm9200996pbc.31.2013.03.15.08.12.00 (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 15 Mar 2013 08:12:03 -0700 (PDT) From: Prabhakar lad To: LAK , DLOS Subject: [PATCH v6 1/2] ARM: davinci: dm365: add support for v4l2 video display Date: Fri, 15 Mar 2013 20:41:42 +0530 Message-ID: <1363360303-15521-2-git-send-email-prabhakar.csengg@gmail.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1363360303-15521-1-git-send-email-prabhakar.csengg@gmail.com> References: <1363360303-15521-1-git-send-email-prabhakar.csengg@gmail.com> CC: LKML X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: Errors-To: davinci-linux-open-source-bounces@linux.davincidsp.com From: Lad, Prabhakar Create platform devices for various video modules like venc,osd, vpbe and v4l2 driver for dm365. Signed-off-by: Lad, Prabhakar --- arch/arm/mach-davinci/board-dm365-evm.c | 4 +- arch/arm/mach-davinci/davinci.h | 2 +- arch/arm/mach-davinci/dm365.c | 203 +++++++++++++++++++++++++++++-- 3 files changed, 195 insertions(+), 14 deletions(-) diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c index c2d4958..cf77c46 100644 --- a/arch/arm/mach-davinci/board-dm365-evm.c +++ b/arch/arm/mach-davinci/board-dm365-evm.c @@ -564,8 +564,6 @@ static struct davinci_uart_config uart_config __initdata = { static void __init dm365_evm_map_io(void) { - /* setup input configuration for VPFE input devices */ - dm365_set_vpfe_config(&vpfe_cfg); dm365_init(); } @@ -597,6 +595,8 @@ static __init void dm365_evm_init(void) davinci_setup_mmc(0, &dm365evm_mmc_config); + dm365_init_video(&vpfe_cfg, NULL); + /* maybe setup mmc1/etc ... _after_ mmc0 */ evm_init_cpld(); diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h index 12d544b..1c2670f 100644 --- a/arch/arm/mach-davinci/davinci.h +++ b/arch/arm/mach-davinci/davinci.h @@ -84,7 +84,7 @@ void __init dm365_init_ks(struct davinci_ks_platform_data *pdata); void __init dm365_init_rtc(void); void dm365_init_spi0(unsigned chipselect_mask, const struct spi_board_info *info, unsigned len); -void dm365_set_vpfe_config(struct vpfe_config *cfg); +int __init dm365_init_video(struct vpfe_config *, struct vpbe_config *); /* DM644x function declarations */ void __init dm644x_init(void); diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 6c39805..ec8b06e 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -40,10 +40,16 @@ #define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */ +#define DM3XX_VDAC_CONFIG 0x01c4002c + +#define DM365_RTC_BASE 0x01c69000 + /* Base of key scan register bank */ #define DM365_KEYSCAN_BASE 0x01c69400 -#define DM365_RTC_BASE 0x01c69000 +#define DM365_OSD_BASE 0x01c71c00 + +#define DM365_VENC_REG_BASE 0x01c71e00 #define DAVINCI_DM365_VC_BASE 0x01d0c000 #define DAVINCI_DMA_VC_TX 2 @@ -56,6 +62,11 @@ #define DM365_EMAC_CNTRL_RAM_OFFSET 0x1000 #define DM365_EMAC_CNTRL_RAM_SIZE 0x2000 +#define DM365_VPSS_CLK_CTRL_ADDR 0x44 +#define DM365_VPSS_VENCCLKEN_ENABLE BIT(3) +#define DM365_VPSS_DACCLKEN_ENABLE BIT(4) +#define DM365_VPSS_PLLC2SYSCLK5_ENABLE BIT(5) + static struct pll_data pll1_data = { .num = 1, .phys_base = DAVINCI_PLL1_BASE, @@ -1226,6 +1237,186 @@ static struct platform_device dm365_isif_dev = { }, }; +static struct resource dm365_osd_resources[] = { + { + .start = DM365_OSD_BASE, + .end = DM365_OSD_BASE + 0x100, + .flags = IORESOURCE_MEM, + }, +}; + +static u64 dm365_video_dma_mask = DMA_BIT_MASK(32); + +static struct platform_device dm365_osd_dev = { + .name = DM365_VPBE_OSD_SUBDEV_NAME, + .id = -1, + .num_resources = ARRAY_SIZE(dm365_osd_resources), + .resource = dm365_osd_resources, + .dev = { + .dma_mask = &dm365_video_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +static struct resource dm365_venc_resources[] = { + { + .start = IRQ_VENCINT, + .end = IRQ_VENCINT, + .flags = IORESOURCE_IRQ, + }, + /* venc registers io space */ + { + .start = DM365_VENC_REG_BASE, + .end = DM365_VENC_REG_BASE + 0x180, + .flags = IORESOURCE_MEM, + }, + /* vdaccfg registers io space */ + { + .start = DM3XX_VDAC_CONFIG, + .end = DM3XX_VDAC_CONFIG + 4, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource dm365_v4l2_disp_resources[] = { + { + .start = IRQ_VENCINT, + .end = IRQ_VENCINT, + .flags = IORESOURCE_IRQ, + }, + /* venc registers io space */ + { + .start = DM365_VENC_REG_BASE, + .end = DM365_VENC_REG_BASE + 0x180, + .flags = IORESOURCE_MEM, + }, +}; + +static int dm365_vpbe_setup_pinmux(enum v4l2_mbus_pixelcode if_type, + int field) +{ + switch (if_type) { + case V4L2_MBUS_FMT_SGRBG8_1X8: + davinci_cfg_reg(DM365_VOUT_FIELD_G81); + davinci_cfg_reg(DM365_VOUT_COUTL_EN); + davinci_cfg_reg(DM365_VOUT_COUTH_EN); + break; + + case V4L2_MBUS_FMT_YUYV10_1X20: + if (field) + davinci_cfg_reg(DM365_VOUT_FIELD); + else + davinci_cfg_reg(DM365_VOUT_FIELD_G81); + davinci_cfg_reg(DM365_VOUT_COUTL_EN); + davinci_cfg_reg(DM365_VOUT_COUTH_EN); + break; + + default: + return -EINVAL; + } + + return 0; +} + +static int dm365_venc_setup_clock(enum vpbe_enc_timings_type type, + unsigned int pclock) +{ + void __iomem *vpss_clkctl_reg; + u32 val; + + vpss_clkctl_reg = DAVINCI_SYSMOD_VIRT(DM365_VPSS_CLK_CTRL_ADDR); + + switch (type) { + case VPBE_ENC_STD: + vpss_enable_clock(VPSS_VENC_CLOCK_SEL, 1); + vpss_enable_clock(VPSS_VPBE_CLOCK, 1); + val = DM365_VPSS_VENCCLKEN_ENABLE | DM365_VPSS_DACCLKEN_ENABLE; + break; + + case VPBE_ENC_DV_TIMINGS: + if (pclock <= 27000000) { + vpss_enable_clock(VPSS_VENC_CLOCK_SEL, 1); + vpss_enable_clock(VPSS_VPBE_CLOCK, 1); + val = DM365_VPSS_VENCCLKEN_ENABLE | + DM365_VPSS_DACCLKEN_ENABLE; + } else { + /* set sysclk4 to output 74.25 MHz from pll1 */ + val = DM365_VPSS_PLLC2SYSCLK5_ENABLE | + DM365_VPSS_DACCLKEN_ENABLE | + DM365_VPSS_VENCCLKEN_ENABLE; + } + break; + + default: + return -EINVAL; + } + writel(val, vpss_clkctl_reg); + + return 0; +} + +static struct platform_device dm365_vpbe_display = { + .name = "vpbe-v4l2", + .id = -1, + .num_resources = ARRAY_SIZE(dm365_v4l2_disp_resources), + .resource = dm365_v4l2_disp_resources, + .dev = { + .dma_mask = &dm365_video_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +struct venc_platform_data dm365_venc_pdata = { + .setup_pinmux = dm365_vpbe_setup_pinmux, + .setup_clock = dm365_venc_setup_clock, +}; + +static struct platform_device dm365_venc_dev = { + .name = DM365_VPBE_VENC_SUBDEV_NAME, + .id = -1, + .num_resources = ARRAY_SIZE(dm365_venc_resources), + .resource = dm365_venc_resources, + .dev = { + .dma_mask = &dm365_video_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = (void *)&dm365_venc_pdata, + }, +}; + +static struct platform_device dm365_vpbe_dev = { + .name = "vpbe_controller", + .id = -1, + .dev = { + .dma_mask = &dm365_video_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +int __init dm365_init_video(struct vpfe_config *vpfe_cfg, + struct vpbe_config *vpbe_cfg) +{ + if (vpfe_cfg || vpbe_cfg) + platform_device_register(&dm365_vpss_device); + + if (vpfe_cfg) { + vpfe_capture_dev.dev.platform_data = vpfe_cfg; + /* Add isif clock alias */ + clk_add_alias("master", dm365_isif_dev.name, + "vpss_master", NULL); + platform_device_register(&dm365_isif_dev); + platform_device_register(&vpfe_capture_dev); + } + if (vpbe_cfg) { + dm365_vpbe_dev.dev.platform_data = vpbe_cfg; + platform_device_register(&dm365_osd_dev); + platform_device_register(&dm365_venc_dev); + platform_device_register(&dm365_vpbe_dev); + platform_device_register(&dm365_vpbe_display); + } + + return 0; +} + static int __init dm365_init_devices(void) { if (!cpu_is_davinci_dm365()) @@ -1239,16 +1430,6 @@ static int __init dm365_init_devices(void) clk_add_alias(NULL, dev_name(&dm365_mdio_device.dev), NULL, &dm365_emac_device.dev); - /* Add isif clock alias */ - clk_add_alias("master", dm365_isif_dev.name, "vpss_master", NULL); - platform_device_register(&dm365_vpss_device); - platform_device_register(&dm365_isif_dev); - platform_device_register(&vpfe_capture_dev); return 0; } postcore_initcall(dm365_init_devices); - -void dm365_set_vpfe_config(struct vpfe_config *cfg) -{ - vpfe_capture_dev.dev.platform_data = cfg; -}