From patchwork Sat Mar 16 10:17:31 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 2281731 Return-Path: X-Original-To: patchwork-davinci@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by patchwork1.kernel.org (Postfix) with ESMTP id 841BB3FC8F for ; Sat, 16 Mar 2013 10:18:05 +0000 (UTC) Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id r2GAI5MD016319 for ; Sat, 16 Mar 2013 05:18:05 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id r2GAI4Wk002502 for ; Sat, 16 Mar 2013 05:18:05 -0500 Received: from dlelxv23.itg.ti.com (172.17.1.198) by dfle73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.1.323.3; Sat, 16 Mar 2013 05:18:04 -0500 Received: from linux.omap.com (dlelxs01.itg.ti.com [157.170.227.31]) by dlelxv23.itg.ti.com (8.13.8/8.13.8) with ESMTP id r2GAI4Aq005912 for ; Sat, 16 Mar 2013 05:18:04 -0500 Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id BFBA88062D for ; Sat, 16 Mar 2013 04:18:04 -0600 (CST) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dflp53.itg.ti.com (dflp53.itg.ti.com [128.247.5.6]) by linux.omap.com (Postfix) with ESMTP id 07C8580626 for ; Sat, 16 Mar 2013 04:17:54 -0600 (CST) Received: from white.ext.ti.com (white.ext.ti.com [192.94.93.38]) by dflp53.itg.ti.com (8.13.8/8.13.8) with ESMTP id r2GAHrgF021241 for ; Sat, 16 Mar 2013 05:17:53 -0500 (CDT) Received: from mail6.bemta7.messagelabs.com (mail6.bemta7.messagelabs.com [216.82.255.55]) by white.ext.ti.com (8.13.7/8.13.7) with ESMTP id r2GAHr26012560 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Sat, 16 Mar 2013 05:17:53 -0500 Received: from [216.82.253.163:38730] by server-12.bemta-7.messagelabs.com id CE/30-13595-1D644415; Sat, 16 Mar 2013 10:17:53 +0000 X-Env-Sender: prabhakar.csengg@gmail.com X-Msg-Ref: server-10.tower-166.messagelabs.com!1363429072!11270665!1 X-Originating-IP: [209.85.192.176] X-SpamReason: No, hits=0.5 required=7.0 tests=BODY_RANDOM_LONG, ML_RADAR_SPEW_LINKS_14,spamassassin: X-StarScan-Received: X-StarScan-Version: 6.8.6.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 19883 invoked from network); 16 Mar 2013 10:17:52 -0000 Received: from mail-pd0-f176.google.com (HELO mail-pd0-f176.google.com) (209.85.192.176) by server-10.tower-166.messagelabs.com with RC4-SHA encrypted SMTP; 16 Mar 2013 10:17:52 -0000 Received: by mail-pd0-f176.google.com with SMTP id t12so400221pdi.35 for ; Sat, 16 Mar 2013 03:17:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=9S38fSyfEAOc1Nu+nSZUMjqcCOIoLN/s4a/IPjL3D/U=; b=uE0DDFoY52S++j5TDMb5Re6wwgdeFfi8qQbR5cVlxJ5gtjQPfNN5SFkyfszWew75Kb R31YhX20gswt5+Ht61O+NAk77c1xasLCH50awdpkZF1a4OpoX6rvp5oAliJyqbnHF0Br t6b1FLS5lNbQWVNZP1KKOL5El1GA5m6refDREvlCN+ExhOnqOLBp3J/xtR12mviyNjOE 0mfHyB3tBl4qz0FarHD4q0LUsujOkgUgJqq7CZ9bzRE/R72CmfsRcAPGWO/9OJ2pKKzU 6J7TV+cteSzvU86xITtajVUFiu97fEDN0t9UVUO5aqjOlvM1EZVo5/kVV7ktIUeWwyH4 eOhw== X-Received: by 10.66.171.108 with SMTP id at12mr603615pac.69.1363429071940; Sat, 16 Mar 2013 03:17:51 -0700 (PDT) Received: from localhost.localdomain ([59.98.241.67]) by mx.google.com with ESMTPS id d7sm13111997pbh.45.2013.03.16.03.17.47 (version=TLSv1 cipher=RC4-SHA bits=128/128); Sat, 16 Mar 2013 03:17:51 -0700 (PDT) From: Prabhakar lad To: LAK , DLOS , Sekhar Nori Subject: [PATCH v5 1/2] ARM: davinci: dm355: add support for v4l2 video display Date: Sat, 16 Mar 2013 15:47:31 +0530 Message-ID: <1363429052-1081-2-git-send-email-prabhakar.csengg@gmail.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1363429052-1081-1-git-send-email-prabhakar.csengg@gmail.com> References: <1363429052-1081-1-git-send-email-prabhakar.csengg@gmail.com> CC: LKML X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: Errors-To: davinci-linux-open-source-bounces+patchwork-davinci=patchwork.kernel.org@linux.davincidsp.com From: Lad, Prabhakar Create platform devices for various video modules like venc,osd, vpbe and v4l2 driver for dm355. Signed-off-by: Lad, Prabhakar --- arch/arm/mach-davinci/board-dm355-evm.c | 4 +- arch/arm/mach-davinci/davinci.h | 2 +- arch/arm/mach-davinci/dm355.c | 202 +++++++++++++++++++++++++++++-- 3 files changed, 197 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c index 147b8e1..37d12cc 100644 --- a/arch/arm/mach-davinci/board-dm355-evm.c +++ b/arch/arm/mach-davinci/board-dm355-evm.c @@ -253,8 +253,6 @@ static struct davinci_uart_config uart_config __initdata = { static void __init dm355_evm_map_io(void) { - /* setup input configuration for VPFE input devices */ - dm355_set_vpfe_config(&vpfe_cfg); dm355_init(); } @@ -344,6 +342,8 @@ static __init void dm355_evm_init(void) davinci_setup_mmc(0, &dm355evm_mmc_config); davinci_setup_mmc(1, &dm355evm_mmc_config); + dm355_init_video(&vpfe_cfg, NULL); + dm355_init_spi0(BIT(0), dm355_evm_spi_info, ARRAY_SIZE(dm355_evm_spi_info)); diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h index 1c2670f..acfe0bb 100644 --- a/arch/arm/mach-davinci/davinci.h +++ b/arch/arm/mach-davinci/davinci.h @@ -74,7 +74,7 @@ void __init dm355_init(void); void dm355_init_spi0(unsigned chipselect_mask, const struct spi_board_info *info, unsigned len); void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata); -void dm355_set_vpfe_config(struct vpfe_config *cfg); +int __init dm355_init_video(struct vpfe_config *, struct vpbe_config *); /* DM365 function declarations */ void __init dm365_init(void); diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index b49c3b7..761fcba 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -36,6 +36,17 @@ #define DM355_UART2_BASE (IO_PHYS + 0x206000) +#define DM3XX_VDAC_CONFIG_BASE 0x01c4002c + +#define DM355_OSD_BASE 0x01c70200 + +#define DM355_VENC_BASE 0x01c70400 + +#define DM355_VPSS_CLK_CTRL_ADDR 0x44 +#define DM355_VPSS_MUXSEL_EXTCLK_ENABLE BIT(1) +#define DM355_VPSS_VENCCLKEN_ENABLE BIT(3) +#define DM355_VPSS_DACCLKEN_ENABLE BIT(4) + /* * Device specific clocks */ @@ -744,11 +755,165 @@ static struct platform_device vpfe_capture_dev = { }, }; -void dm355_set_vpfe_config(struct vpfe_config *cfg) +static struct resource dm355_osd_resources[] = { + { + .start = DM355_OSD_BASE, + .end = DM355_OSD_BASE + 0x180, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device dm355_osd_dev = { + .name = DM355_VPBE_OSD_SUBDEV_NAME, + .id = -1, + .num_resources = ARRAY_SIZE(dm355_osd_resources), + .resource = dm355_osd_resources, + .dev = { + .dma_mask = &vpfe_capture_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +static struct resource dm355_venc_resources[] = { + { + .start = IRQ_VENCINT, + .end = IRQ_VENCINT, + .flags = IORESOURCE_IRQ, + }, + /* venc registers io space */ + { + .start = DM355_VENC_BASE, + .end = DM355_VENC_BASE + 0x180, + .flags = IORESOURCE_MEM, + }, + /* VDAC config register io space */ + { + .start = DM3XX_VDAC_CONFIG_BASE, + .end = DM3XX_VDAC_CONFIG_BASE + 4, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource dm355_v4l2_disp_resources[] = { + { + .start = IRQ_VENCINT, + .end = IRQ_VENCINT, + .flags = IORESOURCE_IRQ, + }, + /* venc registers io space */ + { + .start = DM355_VENC_BASE, + .end = DM355_VENC_BASE + 0x180, + .flags = IORESOURCE_MEM, + }, +}; + +static int dm355_vpbe_setup_pinmux(enum v4l2_mbus_pixelcode if_type, + int field) { - vpfe_capture_dev.dev.platform_data = cfg; + switch (if_type) { + case V4L2_MBUS_FMT_SGRBG8_1X8: + davinci_cfg_reg(DM355_VOUT_FIELD_G70); + break; + + case V4L2_MBUS_FMT_YUYV10_1X20: + /* + * This was VPBE_DIGITAL_IF_YCC16. Replace the enum + * accordingly when the right one gets into open source + */ + if (field) + davinci_cfg_reg(DM355_VOUT_FIELD); + else + davinci_cfg_reg(DM355_VOUT_FIELD_G70); + break; + + default: + return -EINVAL; + } + + davinci_cfg_reg(DM355_VOUT_COUTL_EN); + davinci_cfg_reg(DM355_VOUT_COUTH_EN); + + return 0; } +static inline u32 dm355_reg_modify(void *reg, u32 val, u32 mask) +{ + u32 new_val = (readl(reg) & ~mask) | (val & mask); + + writel(new_val, reg); + + return new_val; +} + +static int dm355_venc_setup_clock(enum vpbe_enc_timings_type type, + unsigned int pclock) +{ + void __iomem *vpss_clk_ctrl_reg; + + vpss_clk_ctrl_reg = DAVINCI_SYSMOD_VIRT(DM355_VPSS_CLK_CTRL_ADDR); + + switch (type) { + case VPBE_ENC_STD: + vpss_enable_clock(VPSS_VENC_CLOCK_SEL, 0); + writel(DM355_VPSS_DACCLKEN_ENABLE | + DM355_VPSS_VENCCLKEN_ENABLE, vpss_clk_ctrl_reg); + break; + + case VPBE_ENC_DV_TIMINGS: + if (pclock > 27000000) + /* + * For HD, use external clock source since we cannot + * support HD mode with internal clocks. + */ + writel(DM355_VPSS_MUXSEL_EXTCLK_ENABLE, + vpss_clk_ctrl_reg); + break; + + default: + return -EINVAL; + } + + return 0; +} + +static struct platform_device dm355_vpbe_display = { + .name = "vpbe-v4l2", + .id = -1, + .num_resources = ARRAY_SIZE(dm355_v4l2_disp_resources), + .resource = dm355_v4l2_disp_resources, + .dev = { + .dma_mask = &vpfe_capture_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +struct venc_platform_data dm355_venc_pdata = { + .setup_pinmux = dm355_vpbe_setup_pinmux, + .setup_clock = dm355_venc_setup_clock, +}; + +static struct platform_device dm355_venc_dev = { + .name = DM355_VPBE_VENC_SUBDEV_NAME, + .id = -1, + .num_resources = ARRAY_SIZE(dm355_venc_resources), + .resource = dm355_venc_resources, + .dev = { + .dma_mask = &vpfe_capture_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = (void *)&dm355_venc_pdata, + }, +}; + +static struct platform_device dm355_vpbe_dev = { + .name = "vpbe_controller", + .id = -1, + .dev = { + .dma_mask = &vpfe_capture_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + /*----------------------------------------------------------------------*/ static struct map_desc dm355_io_desc[] = { @@ -868,19 +1033,40 @@ void __init dm355_init(void) davinci_map_sysmod(); } +int __init dm355_init_video(struct vpfe_config *vpfe_cfg, + struct vpbe_config *vpbe_cfg) +{ + if (vpfe_cfg || vpbe_cfg) + platform_device_register(&dm355_vpss_device); + + if (vpfe_cfg) { + /* Add ccdc clock aliases */ + clk_add_alias("master", dm355_ccdc_dev.name, + "vpss_master", NULL); + clk_add_alias("slave", dm355_ccdc_dev.name, "vpss_slave", NULL); + vpfe_capture_dev.dev.platform_data = vpfe_cfg; + platform_device_register(&dm355_ccdc_dev); + platform_device_register(&vpfe_capture_dev); + } + + if (vpbe_cfg) { + dm355_vpbe_dev.dev.platform_data = vpbe_cfg; + platform_device_register(&dm355_osd_dev); + platform_device_register(&dm355_venc_dev); + platform_device_register(&dm355_vpbe_dev); + platform_device_register(&dm355_vpbe_display); + } + + return 0; +} + static int __init dm355_init_devices(void) { if (!cpu_is_davinci_dm355()) return 0; - /* Add ccdc clock aliases */ - clk_add_alias("master", dm355_ccdc_dev.name, "vpss_master", NULL); - clk_add_alias("slave", dm355_ccdc_dev.name, "vpss_master", NULL); davinci_cfg_reg(DM355_INT_EDMA_CC); platform_device_register(&dm355_edma_device); - platform_device_register(&dm355_vpss_device); - platform_device_register(&dm355_ccdc_dev); - platform_device_register(&vpfe_capture_dev); return 0; }