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Sun, 23 Jun 2013 08:01:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=dvQr1Q8SU6v/HwCubKiKv9tjkaUNbuwuB9ifyNI0yv8=; b=fzTuB3HcoKqupv50tkHQznal/jzaef4M5LrGvlUGJxlHS55dIWb2qH4kEHzYLcGKfc rKbZHc+O7Owl09tS4VyxidPqhT6SwdmilDFKSbpzopI1VMrIXMMB9TUHsJQXgEZ3lm4A GXj5SDFP0+59ZV8kdQFbQ/0pZGY0/Baqu4qdok8oM/oW4tyWi9xCZa6J41vXFBeLR+Tz BJ22VF+H0JOmJTtJvn/WHYyOHGheOB1IO3S9VU8FSCb7KMwhhzaD9A+q2W4KdU1s+t+B jQFEjT4qUfc1rDmTONu+ppXMGpXlwM1h14KCj8zlMPHWSaS+ClYpJr3nYmKoFyoB0ust WSlQ== X-Received: by 10.66.193.166 with SMTP id hp6mr10682487pac.118.1371999660543; Sun, 23 Jun 2013 08:01:00 -0700 (PDT) Received: from localhost.localdomain ([1.23.212.179]) by mx.google.com with ESMTPSA id dc3sm13775600pbc.9.2013.06.23.08.00.54 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 23 Jun 2013 08:00:59 -0700 (PDT) From: Prabhakar Lad To: DLOS , LAK , , Sekhar Nori Subject: [PATCH v3 6/6] ARM: davinci: da850: configure system configuration chip(CFGCHIP3) for emac Date: Sun, 23 Jun 2013 20:30:07 +0530 Message-ID: <1371999607-6483-7-git-send-email-prabhakar.csengg@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1371999607-6483-1-git-send-email-prabhakar.csengg@gmail.com> References: <1371999607-6483-1-git-send-email-prabhakar.csengg@gmail.com> CC: , Heiko Schocher , LKML X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: Errors-To: davinci-linux-open-source-bounces@linux.davincidsp.com X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: "Lad, Prabhakar" This patch makes a common function for to configure emac and calls it appropriately in DT and non DT boot mode. The system configuration chip CFGCHIP3, controls the emac module. This patch appropriately configures this register for emac and sets DA850_MII_MDIO_CLKEN_PIN GPIO pin appropriately. Signed-off-by: Lad, Prabhakar Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: davinci-linux-open-source@linux.davincidsp.com Cc: netdev@vger.kernel.org Cc: devicetree-discuss@lists.ozlabs.org Cc: Sekhar Nori Cc: Heiko Schocher --- Changes for v2: none Changes for v3: a> added a common function in da850.c to configure the CFGCHIP3 chip. arch/arm/mach-davinci/board-da850-evm.c | 36 ++-------------------- arch/arm/mach-davinci/da850.c | 45 ++++++++++++++++++++++++++++ arch/arm/mach-davinci/da8xx-dt.c | 16 ++++++++++ arch/arm/mach-davinci/include/mach/da8xx.h | 1 + 4 files changed, 64 insertions(+), 34 deletions(-) diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 8a24b6c..03dd1df 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -50,7 +50,6 @@ #include #include -#define DA850_EVM_PHY_ID "davinci_mdio-0:00" #define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8) #define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15) @@ -60,8 +59,6 @@ #define DA850_WLAN_EN GPIO_TO_PIN(6, 9) #define DA850_WLAN_IRQ GPIO_TO_PIN(6, 10) -#define DA850_MII_MDIO_CLKEN_PIN GPIO_TO_PIN(2, 6) - static struct mtd_partition da850evm_spiflash_part[] = { [0] = { .name = "UBL", @@ -1033,26 +1030,18 @@ static const short da850_evm_rmii_pins[] = { static int __init da850_evm_config_emac(void) { - void __iomem *cfg_chip3_base; - int ret; - u32 val; struct davinci_soc_info *soc_info = &davinci_soc_info; u8 rmii_en = soc_info->emac_pdata->rmii_en; + int ret; if (!machine_is_davinci_da850_evm()) return 0; - cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG); - - val = __raw_readl(cfg_chip3_base); - if (rmii_en) { - val |= BIT(8); ret = davinci_cfg_reg_list(da850_evm_rmii_pins); pr_info("EMAC: RMII PHY configured, MII PHY will not be" " functional\n"); } else { - val &= ~BIT(8); ret = davinci_cfg_reg_list(da850_evm_mii_pins); pr_info("EMAC: MII PHY configured, RMII PHY will not be" " functional\n"); @@ -1062,28 +1051,7 @@ static int __init da850_evm_config_emac(void) pr_warn("%s: CPGMAC/RMII mux setup failed: %d\n", __func__, ret); - /* configure the CFGCHIP3 register for RMII or MII */ - __raw_writel(val, cfg_chip3_base); - - ret = davinci_cfg_reg(DA850_GPIO2_6); - if (ret) - pr_warn("%s:GPIO(2,6) mux setup failed\n", __func__); - - ret = gpio_request(DA850_MII_MDIO_CLKEN_PIN, "mdio_clk_en"); - if (ret) { - pr_warn("Cannot open GPIO %d\n", DA850_MII_MDIO_CLKEN_PIN); - return ret; - } - - /* Enable/Disable MII MDIO clock */ - gpio_direction_output(DA850_MII_MDIO_CLKEN_PIN, rmii_en); - - soc_info->emac_pdata->phy_id = DA850_EVM_PHY_ID; - - ret = da8xx_register_emac(); - if (ret) - pr_warn("%s: EMAC registration failed: %d\n", __func__, ret); - + da850_config_emac(0, rmii_en); return 0; } device_initcall(da850_evm_config_emac); diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index c43abee..d8021bb 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -1197,6 +1197,51 @@ no_ddrpll_mem: return ret; } +void __init da850_config_emac(u32 dt_mode, u32 rmii_enabled) +{ +#define DA850_MII_MDIO_CLKEN_PIN GPIO_TO_PIN(2, 6) +#define DA850_EVM_PHY_ID "davinci_mdio-0:00" + + void __iomem *cfg_chip3_base; + int ret; + u32 val; + + cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG); + + val = readl(cfg_chip3_base); + + if (rmii_enabled) + val |= BIT(8); + else + val &= ~BIT(8); + + /* configure the CFGCHIP3 register for RMII or MII */ + writel(val, cfg_chip3_base); + + ret = davinci_cfg_reg(DA850_GPIO2_6); + if (ret) + pr_warn("%s:GPIO(2,6) mux setup failed\n", __func__); + + ret = gpio_request(DA850_MII_MDIO_CLKEN_PIN, "mdio_clk_en"); + if (ret) { + pr_warn("Cannot open GPIO %d\n", DA850_MII_MDIO_CLKEN_PIN); + return; + } + + /* Enable/Disable MII MDIO clock */ + gpio_direction_output(DA850_MII_MDIO_CLKEN_PIN, rmii_enabled); + + if (!dt_mode) { + struct davinci_soc_info *soc_info = &davinci_soc_info; + + soc_info->emac_pdata->phy_id = DA850_EVM_PHY_ID; + ret = da8xx_register_emac(); + if (ret) + pr_warn("%s: EMAC registration failed: %d\n", + __func__, ret); + } +} + /* VPIF resource, platform data */ static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32); diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c index 1eb3fa8..ca2443c 100644 --- a/arch/arm/mach-davinci/da8xx-dt.c +++ b/arch/arm/mach-davinci/da8xx-dt.c @@ -56,12 +56,28 @@ static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = { #ifdef CONFIG_ARCH_DAVINCI_DA850 +static void __init da8xx_config_emac(void) +{ + struct device_node *np; + u32 rmii_en = 0; + + np = of_find_compatible_node(NULL, NULL, "ti,davinci-dm6467-emac"); + if (!np) + return; + + of_property_read_u32(np, "ti,davinci-rmii-en", &rmii_en); + + da850_config_emac(1, rmii_en); +} + + static void __init da850_init_machine(void) { of_platform_populate(NULL, of_default_bus_match_table, da850_auxdata_lookup, NULL); da8xx_uart_clk_enable(); + da8xx_config_emac(); } static const char *da850_boards_compat[] __initdata = { diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 78fae15..b01304b 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -109,6 +109,7 @@ int __init da850_register_vpif_capture void da8xx_restart(char mode, const char *cmd); void da8xx_rproc_reserve_cma(void); int da8xx_register_rproc(void); +void da850_config_emac(u32 dt_mode, u32 rmii_enabled); extern struct platform_device da8xx_serial_device; extern struct emac_platform_data da8xx_emac_pdata;