From patchwork Sat May 15 18:16:54 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 99839 Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o4FIJ1OZ000720 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Sat, 15 May 2010 18:19:37 GMT Received: from dlep33.itg.ti.com ([157.170.170.112]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o4FIHjq8030337 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Sat, 15 May 2010 13:17:45 -0500 Received: from linux.omap.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id o4FIHjhs001554; Sat, 15 May 2010 13:17:45 -0500 (CDT) Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id 0E29F80627; Sat, 15 May 2010 13:17:45 -0500 (CDT) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dflp51.itg.ti.com (dflp51.itg.ti.com [128.247.22.94]) by linux.omap.com (Postfix) with ESMTP id 475FD80626 for ; Sat, 15 May 2010 13:17:43 -0500 (CDT) Received: from medina.ext.ti.com (localhost [127.0.0.1]) by dflp51.itg.ti.com (8.13.7/8.13.7) with ESMTP id o4FIHhae017888 for ; Sat, 15 May 2010 13:17:43 -0500 (CDT) Received: from psmtp.com (na3sys009amx188.postini.com [74.125.149.169]) by medina.ext.ti.com (8.13.7/8.13.7) with SMTP id o4FIHfj7004289 for ; Sat, 15 May 2010 13:17:42 -0500 Received: from source ([213.79.90.226]) by na3sys009amx188.postini.com ([74.125.148.10]) with SMTP; Sat, 15 May 2010 11:17:42 PDT Received: (qmail 5048 invoked from network); 15 May 2010 18:17:49 -0000 Received: from unknown (HELO wasted.dev.rtsoft.ru) (192.168.1.70) by 0 with SMTP; 15 May 2010 18:17:49 -0000 To: davinci-linux-open-source@linux.davincidsp.com Subject: [PATCH v6 2/3] DA8xx: CPPI 4.1 platform code Content-Disposition: inline From: Sergei Shtylyov Organization: MontaVista Software Inc. Date: Sat, 15 May 2010 22:16:54 +0400 MIME-Version: 1.0 Message-Id: <201005152216.54242.sshtylyov@ru.mvista.com> X-pstn-neptune: 0/0/0.00/0 X-pstn-levels: (S:39.27721/99.90000 CV:99.9000 FC:95.5390 LC:95.5390 R:95.9108 P:95.9108 M:97.0282 C:98.6951 ) X-pstn-settings: 2 (0.5000:0.5000) s cv gt3 gt2 gt1 r p m c X-pstn-addresses: from [db-null] Cc: linux-arm-kernel@lists.infradead.org X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: davinci-linux-open-source-bounces@linux.davincidsp.com Errors-To: davinci-linux-open-source-bounces@linux.davincidsp.com X-Greylist: Sender succeeded STARTTLS authentication, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 15 May 2010 18:19:37 +0000 (UTC) Index: linux-davinci/arch/arm/mach-davinci/Kconfig =================================================================== --- linux-davinci.orig/arch/arm/mach-davinci/Kconfig +++ linux-davinci/arch/arm/mach-davinci/Kconfig @@ -32,12 +32,14 @@ config ARCH_DAVINCI_DM646x config ARCH_DAVINCI_DA830 bool "DA830/OMAP-L137 based system" select CP_INTC + select TI_CPPI41 select ARCH_DAVINCI_DA8XX select CPU_DCACHE_WRITETHROUGH # needed on silicon revs 1.0, 1.1 config ARCH_DAVINCI_DA850 bool "DA850/OMAP-L138 based system" select CP_INTC + select TI_CPPI41 select ARCH_DAVINCI_DA8XX select ARCH_HAS_CPUFREQ Index: linux-davinci/arch/arm/mach-davinci/include/mach/da8xx.h =================================================================== --- linux-davinci.orig/arch/arm/mach-davinci/include/mach/da8xx.h +++ linux-davinci/arch/arm/mach-davinci/include/mach/da8xx.h @@ -67,6 +67,8 @@ extern void __iomem *da8xx_syscfg1_base; void __init da830_init(void); void __init da850_init(void); +int da8xx_cppi41_init(void); + int da8xx_register_edma(void); int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata); int da8xx_register_watchdog(void); Index: linux-davinci/arch/arm/mach-davinci/usb.c =================================================================== --- linux-davinci.orig/arch/arm/mach-davinci/usb.c +++ linux-davinci/arch/arm/mach-davinci/usb.c @@ -2,11 +2,14 @@ * USB */ #include +#include #include #include #include +#include + #include #include #include @@ -173,4 +176,107 @@ int __init da8xx_register_usb11(struct d da8xx_usb11_device.dev.platform_data = pdata; return platform_device_register(&da8xx_usb11_device); } + +static const struct cppi41_tx_ch tx_ch_info[] = { + [0] = { + .port_num = 1, + .num_tx_queue = 2, + .tx_queue = { { 0, 16 }, { 0, 17 } } + }, + [1] = { + .port_num = 2, + .num_tx_queue = 2, + .tx_queue = { { 0, 18 }, { 0, 19 } } + }, + [2] = { + .port_num = 3, + .num_tx_queue = 2, + .tx_queue = { { 0, 20 }, { 0, 21 } } + }, + [3] = { + .port_num = 4, + .num_tx_queue = 2, + .tx_queue = { { 0, 22 }, { 0, 23 } } + } +}; + +/* DMA block configuration */ +const struct cppi41_dma_block cppi41_dma_block[1] = { + [0] = { + .global_ctrl_base = IO_ADDRESS(DA8XX_USB0_BASE + 0x1000), + .ch_ctrl_stat_base = IO_ADDRESS(DA8XX_USB0_BASE + 0x1800), + .sched_ctrl_base = IO_ADDRESS(DA8XX_USB0_BASE + 0x2000), + .sched_table_base = IO_ADDRESS(DA8XX_USB0_BASE + 0x2800), + .num_tx_ch = 4, + .num_rx_ch = 4, + .tx_ch_info = tx_ch_info + } +}; +EXPORT_SYMBOL(cppi41_dma_block); + +/* Queues 0 to 27 are pre-assigned, others are spare */ +static const unsigned long assigned_queues[] = { 0x0fffffff, 0 }; + +/* Queue manager information */ +const struct cppi41_queue_mgr cppi41_queue_mgr[1] = { + [0] = { + .q_mgr_rgn_base = IO_ADDRESS(DA8XX_USB0_BASE + 0x4000), + .desc_mem_rgn_base = IO_ADDRESS(DA8XX_USB0_BASE + 0x5000), + .q_mgmt_rgn_base = IO_ADDRESS(DA8XX_USB0_BASE + 0x6000), + .q_stat_rgn_base = IO_ADDRESS(DA8XX_USB0_BASE + 0x6800), + + .num_queue = 64, + .queue_types = CPPI41_FREE_DESC_BUF_QUEUE | + CPPI41_UNASSIGNED_QUEUE, + .base_fdbq_num = 0, + .assigned = assigned_queues + } +}; +EXPORT_SYMBOL(cppi41_queue_mgr); + +const u8 cppi41_num_queue_mgr = 1; +const u8 cppi41_num_dma_block = 1; + +/* Fair DMA scheduling */ +static const u8 dma_sched_table[] = { + 0x00, 0x80, 0x01, 0x81, 0x02, 0x82, 0x03, 0x83 +}; + +int __init da8xx_cppi41_init(void) +{ + struct clk *usb20_clk; + int ret; + + /* CPPI 4.1 is clocked by USB 2.0 clock. */ + usb20_clk = clk_get(NULL, "usb20"); + if (IS_ERR(usb20_clk)) { + ret = PTR_ERR(usb20_clk); + pr_warning("%s: clk_get() call failed: %d\n", __func__, ret); + return ret; + } + clk_enable(usb20_clk); + + /* We provide no memory for the queue manager's linking RAM region 0. */ + ret = cppi41_queue_mgr_init(0, 0, 0); + if (ret) { + pr_warning("%s: queue manager initialization failed: %d\n", + __func__, ret); + return ret; + } + + /* Allocate 32 (2^5) DMA teardown descriptors from queue manager 0. */ + ret = cppi41_dma_ctrlr_init(0, 0, 5); + if (ret) { + pr_warning("%s: DMA controller initialization failed: %d\n", + __func__, ret); + return ret; + } + + ret = cppi41_dma_sched_init(0, dma_sched_table, + sizeof(dma_sched_table)); + if (ret) + pr_warning("%s: DMA scheduler initialization failed: %d\n", + __func__, ret); + return ret; +} #endif /* CONFIG_DAVINCI_DA8XX */