From patchwork Wed Nov 6 11:33:03 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 3146751 Return-Path: X-Original-To: patchwork-davinci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id CC0CDBEEB2 for ; Wed, 6 Nov 2013 11:36:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7881F200E6 for ; Wed, 6 Nov 2013 11:36:28 +0000 (UTC) Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A7CBB200D5 for ; Wed, 6 Nov 2013 11:36:23 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id rA6BaNt1024809 for ; Wed, 6 Nov 2013 05:36:23 -0600 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id rA6BaMX4000810 for ; Wed, 6 Nov 2013 05:36:22 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.2.342.3; Wed, 6 Nov 2013 05:36:22 -0600 Received: from linux.omap.com (dlelxs01.itg.ti.com [157.170.227.31]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id rA6BaMbP022514 for ; Wed, 6 Nov 2013 05:36:22 -0600 Received: from linux.omap.com (localhost [127.0.0.1]) by linux.omap.com (Postfix) with ESMTP id 1A3C680627 for ; Wed, 6 Nov 2013 05:36:22 -0600 (CST) X-Original-To: davinci-linux-open-source@linux.davincidsp.com Delivered-To: davinci-linux-open-source@linux.davincidsp.com Received: from dflxv15.itg.ti.com (dflxv15.itg.ti.com [128.247.5.124]) by linux.omap.com (Postfix) with ESMTP id F01B280626 for ; Wed, 6 Nov 2013 05:35:30 -0600 (CST) Received: from DNCE70.ent.ti.com (dncmailx.itg.ti.com [137.167.131.19]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id rA6BZTvH030685; Wed, 6 Nov 2013 05:35:30 -0600 Received: from [10.167.145.75] (10.167.145.75) by DNCE70.ent.ti.com (137.167.131.19) with Microsoft SMTP Server id 14.2.342.3; Wed, 6 Nov 2013 12:35:29 +0100 Message-ID: <527A28EF.9070601@ti.com> Date: Wed, 6 Nov 2013 13:33:03 +0200 From: Grygorii Strashko User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.1.0 MIME-Version: 1.0 To: Sekhar Nori , Prabhakar Lad , Linus Walleij Subject: Re: [PATCH v4 1/6] gpio: davinci: Fixed a check for unbanked gpio References: <1383406775-14902-1-git-send-email-prabhakar.csenng@gmail.com> <1383406775-14902-2-git-send-email-prabhakar.csenng@gmail.com> <527A1EC7.20400@ti.com> In-Reply-To: <527A1EC7.20400@ti.com> X-Originating-IP: [10.167.145.75] X-EXCLAIMER-MD-CONFIG: f9c360f5-3d1e-4c3c-8703-f45bf52eff6b CC: Mark Rutland , "devicetree@vger.kernel.org" , "davinci-linux-open-source@linux.davincidsp.com" , Russell King , Pawel Moll , "linux-doc@vger.kernel.org" , Stephen Warren , "linux-kernel@vger.kernel.org" , Rob Herring , "linux-gpio@vger.kernel.org" , Rob Landley , Alex Elder , Grant Likely , Ian Campbell , "linux-arm-kernel@lists.infradead.org" X-BeenThere: davinci-linux-open-source@linux.davincidsp.com X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: Errors-To: davinci-linux-open-source-bounces+patchwork-davinci=patchwork.kernel.org@linux.davincidsp.com X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hi Sekhar, Linus, On 11/06/2013 12:49 PM, Sekhar Nori wrote: > On Wednesday 06 November 2013 03:45 PM, Prabhakar Lad wrote: >> Hi Linus, >> >> On Wed, Nov 6, 2013 at 3:26 PM, Linus Walleij wrote: >>> On Wed, Nov 6, 2013 at 10:33 AM, Prabhakar Lad >>> wrote: >>>> On Tue, Nov 5, 2013 at 6:09 PM, Linus Walleij wrote: >>>>> On Sat, Nov 2, 2013 at 4:39 PM, Lad, Prabhakar >>>>> wrote: >>>>> >>>>>> From: "Lad, Prabhakar" >>>>>> >>>>>> This patch fixes the check for the offset in >>>>>> gpio_to_irq_unbanked() function. >>>>>> >>>>>> Signed-off-by: Lad, Prabhakar >>>>> >>>>> Is this a regression that should go in right now? >>>>> >>>> Yes it needs too. >>> >>> But on top of *what* exactly? >>> >>> This does not apply to my gpio tree devel branch and >>> not even on the mainline kernel. >>> >> Looks like this needs to go via ARM tree as the earlier >> patches have gone via ARM tree itself [1]. >> If you can ACK it Sekhar can get it in via ARM tree. > > The dependent patches are all in linux-next through ARM SoC queued for > v3.13 merge. This fix can either be sent late in merge cycle once Linus > has pulled ARM SoC or after v3.13-rc1 comes out. Pls, wait a bit - this fix is incomplete :( The below changes have to be done too: Regards, - grygorii diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c index 6c90cfb..05dbadb 100644 --- a/drivers/gpio/gpio-davinci.c +++ b/drivers/gpio/gpio-davinci.c @@ -328,7 +328,7 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). */ if (offset < d->gpio_unbanked) - return d->gpio_irq + offset; + return d->irq_base + offset; else return -ENODEV; } @@ -341,7 +341,7 @@ static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger) d = (struct davinci_gpio_controller *)data->handler_data; g = (struct davinci_gpio_regs __iomem *)d->regs; - mask = __gpio_mask(data->irq - d->gpio_irq); + mask = __gpio_mask(data->irq - d->irq_base); if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) return -EINVAL; @@ -419,6 +419,8 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev) /* pass "bank 0" GPIO IRQs to AINTC */ chips[0].chip.to_irq = gpio_to_irq_unbanked; + chips[0].irq_base = bank_irq; + chips[0].gpio_unbanked = pdata->gpio_unbanked; binten = BIT(0); /* AINTC handles mask/unmask; GPIO handles triggering */ diff --git a/include/linux/platform_data/gpio-davinci.h b/include/linux/platform_data/gpio-davinci.h index 6efd202..711a002 100644 --- a/include/linux/platform_data/gpio-davinci.h +++ b/include/linux/platform_data/gpio-davinci.h @@ -42,7 +42,6 @@ struct davinci_gpio_controller { void __iomem *clr_data; void __iomem *in_data; int gpio_unbanked; - unsigned gpio_irq; }; ================================================================== Also all places where davinci_gpio_register() is called need to be updated to use instead of "sizeof". Like: diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index ef9ff1f..10334a4 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -906,8 +906,8 @@ static struct davinci_gpio_platform_data dm355_gpio_platform_data = { int __init dm355_gpio_register(void) { return davinci_gpio_register(dm355_gpio_resources, - sizeof(dm355_gpio_resources), - &dm355_gpio_platform_data); + ARRAY_SIZE(dm355_gpio_resources), + &dm355_gpio_platform_data); }