Message ID | 87k4eo6d5m.fsf@ti.com (mailing list archive) |
---|---|
State | Awaiting Upstream |
Headers | show |
Hi Trinabh, Trinabh Gupta <trinabh@linux.vnet.ibm.com> writes: [...] > I just wanted to get comments on the design and understand how it > affects various architectures in question. It looks to me as if the > design should be okay and infact better for architectures like ARM > since they do not have different idle states for different cpus and > thus do not require per-cpu registration. Global registration would > work and be simpler; please correct me if I am wrong. Yes, I agree that the new design is better, I especially like that it's more clear (and expected) that final state decision making is to be done directly in the driver without the back-and-forth in the current setup. Thanks, Kevin
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index 6641574..ab77ba3 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -512,6 +512,7 @@ static int omap3_cpuidle_driver_init(void) int i, retval, count = 0; struct omap3_processor_cx *cx; struct cpuidle_state *state; + struct cpuidle_driver *drv = &omap3_idle_driver; mpu_pd = pwrdm_lookup("mpu_pwrdm"); core_pd = pwrdm_lookup("core_pwrdm"); @@ -532,7 +533,7 @@ static int omap3_cpuidle_driver_init(void) state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ? omap3_enter_idle_bm : omap3_enter_idle; if (cx->type == OMAP3_STATE_C1) - dev->safe_state_index = count; + drv->safe_state_index = count; sprintf(state->name, "C%d", count+1); strncpy(state->desc, cx->desc, CPUIDLE_DESC_LEN); count++;