dm365 - davincifb with rgb lcd

Commit Message

Raffaele Recalcati April 16, 2010, 10:25 a.m. UTC

None

Patch

diff --git a/include/video/davincifb.h b/include/video/davincifb.h
index 96b5c20..33a2b70 100644
--- a/include/video/davincifb.h
+++ b/include/video/davincifb.h
@@ -16,10 +16,16 @@ 
 #include <mach/io.h>

 /* Base registers */
+#if 0
 #define        VPBE_REG_BASE                           0x01c72780
 #define        VENC_REG_BASE                           0x01c72400
 #define        OSD_REG_BASE                            0x01c72600
 #define OSD_REG_SIZE                           0x00000180
+#endif
+
+#define VENC_REG_BASE                           0x01C71E00
+#define OSD_REG_BASE                            0x01C71C00
+#define OSD_REG_SIZE                           0x00000100

 /* VPBE Global Registers */
 #define        VPBE_PID                                (VPBE_BASE + 0x0)

Then we have tried to add rgb support to davincifb.c.
The kernel starts if you use
video=davincifb:output=lcd:format=rgb:vid0=240x320@0,0:vid1=320x240@0
,0:osd0=240x320@0,0
osd0_default_var contains the setting for our lcd, but we should pass these
parameters from board file, but we don't know how to do it.

diff --git a/drivers/video/davincifb.c b/drivers/video/davincifb.c
index 1344be7..31dc147 100644
--- a/drivers/video/davincifb.c
+++ b/drivers/video/davincifb.c
@@ -171,14 +171,15 @@  static struct fb_var_screeninfo osd0_default_var = {
        .width = -1,
        .accel_flags = 0,
        .pixclock = LCD_PANEL_CLOCK,    /* picoseconds */
-       .left_margin = 40,      /* pixclocks */
-       .right_margin = 4,      /* pixclocks */
-       .upper_margin = 8,      /* line clocks */
-       .lower_margin = 2,      /* line clocks */
-       .hsync_len = 4,         /* pixclocks */
-       .vsync_len = 2,         /* line clocks */
+       .left_margin = 18,      /* pixclocks */
+       .right_margin = 12,     /* pixclocks */
+       .upper_margin = 20,     /* line clocks */
+       .lower_margin = 8,      /* line clocks */
+       .hsync_len = 1,         /* pixclocks */
+       .vsync_len = 1,         /* line clocks */
        .sync = 0,
-       .vmode = FB_VMODE_INTERLACED,
+/*     .vmode = FB_VMODE_INTERLACED,*/
+       .vmode = FB_VMODE_NONINTERLACED,
 };

 /* Using the full screen for OSD1 by default */
@@ -1394,6 +1395,52 @@  static void davincifb_pal_component_config(int on)
        }
 }

+static void davincifb_lcd_rgb_config(int on)
+{
+       printk("%s %d\n", __func__, __LINE__);
+        if (on) {
+                /* Reset video encoder module */
+       printk("%s %d\n", __func__, __LINE__);
+       printk("writing %X to register having address:%X\n", 0x25D3,
VENC_VMOD);
+                dispc_reg_out(VENC_VMOD, 0x25D3);
+
+                /* set hsync pulse width */
+                dispc_reg_out(VENC_HSPLS, dm->osd1->info.var.hsync_len);
+
+                /* set vsync pulse width */
+                dispc_reg_out(VENC_VSPLS, dm->osd1->info.var.vsync_len);
+
+                /* set horizontal interval  */
+                dispc_reg_out(VENC_HINT, dm->osd1->info.var.left_margin +
dm->osd1->info.var.right_margin + dm->osd1-
+
+                /* set horizontal data valid start position  */
+                dispc_reg_out(VENC_HSTART, dm->osd1->info.var.left_margin);
+
+                /* set Horizontal data valid range  */
+                dispc_reg_out(VENC_HVALID, dm->osd1->info.var.width);
+
+                /* set Vertical interval  */
+                dispc_reg_out(VENC_VINT, dm->osd1->info.var.upper_margin +
dm->osd1->info.var.lower_margin + dm->osd1
+
+                /* set Vertical data valid start position */
+                dispc_reg_out(VENC_HVALID,
dm->osd1->info.var.upper_margin);
+
+                /* set Horizontal data valid range  */
+                dispc_reg_out(VENC_VVALID, dm->osd1->info.var.height);
+#if 0
+                /* set Horizontal sync delay */
+                dispc_reg_out(VENC_HVALID, dm->osd1->info.??);
+
+                /* set vertical sync delay */
+                dispc_reg_out(VENC_HVALID, dm->osd1->info.var.??);
+#endif
+        } else {
+                /* Reset video encoder module */
+                dispc_reg_out(VENC_VMOD, 0);
+        }
+}
+