From patchwork Fri Sep 28 08:36:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Yves MORDRET X-Patchwork-Id: 10619161 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D8C8014BD for ; Fri, 28 Sep 2018 08:37:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CB7142A793 for ; Fri, 28 Sep 2018 08:37:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BEDAB2A783; Fri, 28 Sep 2018 08:37:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 340772A783 for ; Fri, 28 Sep 2018 08:37:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728901AbeI1O7s (ORCPT ); Fri, 28 Sep 2018 10:59:48 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:29686 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728275AbeI1O7s (ORCPT ); Fri, 28 Sep 2018 10:59:48 -0400 Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w8S8YLHW031526; Fri, 28 Sep 2018 10:36:42 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2mrj4mhvx4-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Fri, 28 Sep 2018 10:36:42 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id DF54831; Fri, 28 Sep 2018 08:36:41 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag5node2.st.com [10.75.127.14]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A6DEB262C; Fri, 28 Sep 2018 08:36:41 +0000 (GMT) Received: from localhost (10.75.127.46) by SFHDAG5NODE2.st.com (10.75.127.14) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Fri, 28 Sep 2018 10:36:41 +0200 From: Pierre-Yves MORDRET To: Vinod Koul , Rob Herring , Mark Rutland , Alexandre Torgue , Maxime Coquelin , Dan Williams , , , , CC: Pierre-Yves MORDRET Subject: [PATCH v2 0/7] Add-DMA-MDMA-chaining-support Date: Fri, 28 Sep 2018 10:36:27 +0200 Message-ID: <1538123794-17085-1-git-send-email-pierre-yves.mordret@st.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [10.75.127.46] X-ClientProxiedBy: SFHDAG5NODE1.st.com (10.75.127.13) To SFHDAG5NODE2.st.com (10.75.127.14) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2018-09-28_03:,, signatures=0 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This serie adds support for M2M transfer triggered by STM32 DMA in order to transfer data from/to SRAM to/from DDR. Normally, this mode should not be needed as transferring data from/to DDR is supported by the STM32 DMA. However, the STM32 DMA don't have the ability to generate burst transfer on the DDR as it only embeds only a 4-word FIFO although the minimal burst length on the DDR is 8 words. Due to this constraint, the STM32 DMA transfers data from/to DDR in a single way and could lead to pollute the DDR. To avoid this, we have to use SRAM for all transfers where STM32 DMA is involved. An Hw design has been specially put in place to allow this chaining where DMA interrupt is connected on GIC and MDMA request line as well. This grants the possibility to trigger an MDMA transfer from the completion of DMA. At the same time MDMA has the ability to acknowlege DMA. The aim is to have an self refreching mechanism to transfer from/to device to/from DDR with minimal sw support. For instance the DMA is set in cyclic double buffering to feed SRAM and MDMA transfer to DDR thanks to LLI. M'boumba Cedric Madianga (7): dt-bindings: stm32-dma: Add DMA/MDMA chaining support bindings dt-bindings: stm32-dmamux: Add one cell to support DMA/MDMA chain dt-bindings: stm32-mdma: Add DMA/MDMA chaining support bindings dmaengine: stm32-dma: Add DMA/MDMA chaining support dmaengine: stm32-mdma: Add DMA/MDMA chaining support dmaengine: stm32-dma: enable descriptor_reuse dmaengine: stm32-mdma: enable descriptor_reuse .../devicetree/bindings/dma/stm32-dma.txt | 27 +- .../devicetree/bindings/dma/stm32-dmamux.txt | 6 +- .../devicetree/bindings/dma/stm32-mdma.txt | 12 +- drivers/dma/stm32-dma.c | 903 ++++++++++++++++++--- drivers/dma/stm32-mdma.c | 133 ++- 5 files changed, 949 insertions(+), 132 deletions(-)