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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Sep 2022 15:53:08.3697 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 69d02973-ef19-44d2-4611-08da95a00dc9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.238];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6337 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Read dma-channel-mask from device tree and register only the specified channels. This is useful to reserve some channels for the firmware. Also update the channel number and interrupts to include all 32 channels. The current driver was using only 31 channels as one channel was reserved for firmware. Now with this change, the driver can align more to the actual hardware. Akhil R (3): dt-bindings: dmaengine: Add dma-channel-mask to Tegra GPCDMA arm64: tegra: Add dma-channel-mask in GPCDMA node dmaengine: tegra: Add support for dma-channel-mask .../bindings/dma/nvidia,tegra186-gpc-dma.yaml | 7 +++- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 4 ++- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 ++- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 4 ++- drivers/dma/tegra186-gpc-dma.c | 35 +++++++++++++++---- 5 files changed, 44 insertions(+), 10 deletions(-)