| Message ID | 20230323034944.78357-1-cai.huoqing@linux.dev (mailing list archive) |
|---|---|
| Headers | show |
| Series | dmaengine: dw-edma: Add support for native HDMA | expand |
On Thu, Mar 23, 2023 at 11:49:37AM +0800, Cai Huoqing wrote: > Add support for HDMA NATIVE, as long the IP design has set > the compatible register map parameter-HDMA_NATIVE, > which allows compatibility for native HDMA register configuration. > > The HDMA Hyper-DMA IP is an enhancement of the eDMA embedded-DMA IP. > And the native HDMA registers are different from eDMA, > so this patch add support for HDMA NATIVE mode. > > HDMA write and read channels operate independently to maximize > the performance of the HDMA read and write data transfer over > the link When you configure the HDMA with multiple read channels, > then it uses a round robin (RR) arbitration scheme to select > the next read channel to be serviced.The same applies when > youhave multiple write channels. > > The native HDMA driver also supports a maximum of 16 independent > channels (8 write + 8 read), which can run simultaneously. > Both SAR (Source Address Register) and DAR (Destination Address Register) > are aligned to byte. > > Cai Huoqing (1): > dmaengine: dw-edma: Add support for native HDMA > > Cai huoqing (3): > dmaengine: dw-edma: Rename dw_edma_core_ops structure to > dw_edma_plat_ops > dmaengine: dw-edma: Create a new dw_edma_core_ops structure to > abstract controller operation > dmaengine: dw-edma: Add HDMA DebugFS support > > v7->v8: > 1.Remove the [5/5] patch in v7. > [3/4] > 2.Get back the static methods: dw_hdma_v0_core_clear_done_int(), > dw_hdma_v0_core_clear_abort_int() and dw_hdma_v0_core_status_int(). > [4/4] > 3.Drop some unused field in dw_hdma_debugfs_entry. The whole series looking good now except a few nitpicks which can be fixed should v9 is required (see patches #3 and #4). I've got the patchset tested on DW PCIe Root Port v4.60a with eDMA engine embedded. A dummy read/write DMA-streams from/to a remote PCIe VGA adapter memory was performed as expected. So feel free to add to the entire series: Tested-by: Serge Semin <fancer.lancer@gmail.com> -Serge(y) > > v7 link: > https://lore.kernel.org/lkml/20230315012840.6986-1-cai.huoqing@linux.dev/ > > drivers/dma/dw-edma/Makefile | 8 +- > drivers/dma/dw-edma/dw-edma-core.c | 86 ++---- > drivers/dma/dw-edma/dw-edma-core.h | 58 ++++ > drivers/dma/dw-edma/dw-edma-pcie.c | 4 +- > drivers/dma/dw-edma/dw-edma-v0-core.c | 85 +++++- > drivers/dma/dw-edma/dw-edma-v0-core.h | 14 +- > drivers/dma/dw-edma/dw-hdma-v0-core.c | 296 +++++++++++++++++++ > drivers/dma/dw-edma/dw-hdma-v0-core.h | 17 ++ > drivers/dma/dw-edma/dw-hdma-v0-debugfs.c | 173 +++++++++++ > drivers/dma/dw-edma/dw-hdma-v0-debugfs.h | 22 ++ > drivers/dma/dw-edma/dw-hdma-v0-regs.h | 130 ++++++++ > drivers/pci/controller/dwc/pcie-designware.c | 2 +- > include/linux/dma/edma.h | 7 +- > 13 files changed, 811 insertions(+), 91 deletions(-) > create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-core.c > create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-core.h > create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-debugfs.c > create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-debugfs.h > create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-regs.h > > -- > 2.34.1 >
Add support for HDMA NATIVE, as long the IP design has set the compatible register map parameter-HDMA_NATIVE, which allows compatibility for native HDMA register configuration. The HDMA Hyper-DMA IP is an enhancement of the eDMA embedded-DMA IP. And the native HDMA registers are different from eDMA, so this patch add support for HDMA NATIVE mode. HDMA write and read channels operate independently to maximize the performance of the HDMA read and write data transfer over the link When you configure the HDMA with multiple read channels, then it uses a round robin (RR) arbitration scheme to select the next read channel to be serviced.The same applies when youhave multiple write channels. The native HDMA driver also supports a maximum of 16 independent channels (8 write + 8 read), which can run simultaneously. Both SAR (Source Address Register) and DAR (Destination Address Register) are aligned to byte. Cai Huoqing (1): dmaengine: dw-edma: Add support for native HDMA Cai huoqing (3): dmaengine: dw-edma: Rename dw_edma_core_ops structure to dw_edma_plat_ops dmaengine: dw-edma: Create a new dw_edma_core_ops structure to abstract controller operation dmaengine: dw-edma: Add HDMA DebugFS support v7->v8: 1.Remove the [5/5] patch in v7. [3/4] 2.Get back the static methods: dw_hdma_v0_core_clear_done_int(), dw_hdma_v0_core_clear_abort_int() and dw_hdma_v0_core_status_int(). [4/4] 3.Drop some unused field in dw_hdma_debugfs_entry. v7 link: https://lore.kernel.org/lkml/20230315012840.6986-1-cai.huoqing@linux.dev/ drivers/dma/dw-edma/Makefile | 8 +- drivers/dma/dw-edma/dw-edma-core.c | 86 ++---- drivers/dma/dw-edma/dw-edma-core.h | 58 ++++ drivers/dma/dw-edma/dw-edma-pcie.c | 4 +- drivers/dma/dw-edma/dw-edma-v0-core.c | 85 +++++- drivers/dma/dw-edma/dw-edma-v0-core.h | 14 +- drivers/dma/dw-edma/dw-hdma-v0-core.c | 296 +++++++++++++++++++ drivers/dma/dw-edma/dw-hdma-v0-core.h | 17 ++ drivers/dma/dw-edma/dw-hdma-v0-debugfs.c | 173 +++++++++++ drivers/dma/dw-edma/dw-hdma-v0-debugfs.h | 22 ++ drivers/dma/dw-edma/dw-hdma-v0-regs.h | 130 ++++++++ drivers/pci/controller/dwc/pcie-designware.c | 2 +- include/linux/dma/edma.h | 7 +- 13 files changed, 811 insertions(+), 91 deletions(-) create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-core.c create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-core.h create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-debugfs.c create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-debugfs.h create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-regs.h