From patchwork Fri Dec 8 10:38:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: shravan chippa X-Patchwork-Id: 13485282 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="kK93Qyvk" Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 025AD123; Fri, 8 Dec 2023 02:37:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1702031877; x=1733567877; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=7TMZPFXosBz7PqjBl5YlGhmPAW3iNWnMHeI86fag7dg=; b=kK93Qyvkf3gUMOv1ZAZfxPWoxr8BioUAu0irQoKp90OnLDMSQXGmFg8E Pjn9XGuwlS3d9jmGXJWXLxbdwmzAel2L+tsVbaQdv+NUzdi8VSuDdoL2S NoBIPCLZNvH2Wna37xIKAsb6wmhphFAbsBQ0oOnI3jNlRxTxUr/2BLbUu cEskEK1xY9tBDnRO6P0K1aoFGdsuXhO+Pb8Ngd9OhRIDQZk0+584DerHf uzH0CE8aU3volcTE8jmgaMearcdk+3+yjihHJhV2AmXfoQJlwgbhQ15eI wW41ySMg9XgvExhBJnSOaO8CSc6ypg+rwN3k6fZyNk5yi+x3KZLURvDgl A==; X-CSE-ConnectionGUID: H3XQVRBZQ2qxsVmz7vJ8Sw== X-CSE-MsgGUID: vh62aFwNTVOODghp70fLHA== X-ThreatScanner-Verdict: Negative X-IronPort-AV: E=Sophos;i="6.04,260,1695711600"; d="scan'208";a="13315272" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 08 Dec 2023 03:37:49 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 8 Dec 2023 03:37:44 -0700 Received: from microchip1-OptiPlex-9020.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 8 Dec 2023 03:37:39 -0700 From: shravan chippa To: , , , , , , CC: , , , , , , Subject: [PATCH v5 0/4] dma: sf-pdma: various sf-pdma updates for the mpfs platform Date: Fri, 8 Dec 2023 16:08:52 +0530 Message-ID: <20231208103856.3732998-1-shravan.chippa@microchip.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Shravan Chippa Changes from V4 -> V5: Modified commit msg Replaced the sf_pdma_of_xlate() function with of_dma_xlate_by_chan_id() Changes from V3 -> V4: Removed unnecessary parentheses and extra space Added review tags Changes from V2 -> V3: Removed whitespace Change naming convention of the macros (modified code as per new macros) updated with new API device_get_match_data() modified dt-bindings as per the commmets from v2 modified compatible name string for mpfs platform Changes from V1 -> V2: Removed internal review tags Commit massages modified. Added devicetree patch with new compatible name for mpfs platform Added of_dma_controller_free() clenup call in sf_pdma_remove() function V1: This series does the following 1. Adds a PolarFire SoC specific compatible and code to support for out-of-order dma transfers 2. Adds generic device tree bindings support by using of_dma_controller_register() Shravan Chippa (4): dmaengine: sf-pdma: Support of_dma_controller_register() dt-bindings: dma: sf-pdma: add new compatible name dmaengine: sf-pdma: add mpfs-pdma compatible name riscv: dts: microchip: add specific compatible for mpfs pdma .../bindings/dma/sifive,fu540-c000-pdma.yaml | 1 + arch/riscv/boot/dts/microchip/mpfs.dtsi | 2 +- drivers/dma/sf-pdma/sf-pdma.c | 44 +++++++++++++++++-- drivers/dma/sf-pdma/sf-pdma.h | 8 +++- 4 files changed, 50 insertions(+), 5 deletions(-)