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Thu, 29 Aug 2024 09:24:45 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 47T9Oios017508; Thu, 29 Aug 2024 09:24:45 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-msavaliy-hyd.qualcomm.com [10.213.110.207]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 47T9OikD017246 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 09:24:44 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 429934) id A5FC5240D0; Thu, 29 Aug 2024 14:54:43 +0530 (+0530) From: Mukesh Kumar Savaliya To: konrad.dybcio@linaro.org, andersson@kernel.org, andi.shyti@kernel.org, linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org Cc: quic_vdadhani@quicinc.com, Mukesh Kumar Savaliya Subject: [PATCH v1 0/4] Enable shared SE support over I2C Date: Thu, 29 Aug 2024 14:54:14 +0530 Message-Id: <20240829092418.2863659-1-quic_msavaliy@quicinc.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: SN0ZsRaGfyXrJKAyerQpF4wqhoLMHHGA X-Proofpoint-ORIG-GUID: SN0ZsRaGfyXrJKAyerQpF4wqhoLMHHGA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-29_02,2024-08-29_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=537 bulkscore=0 impostorscore=0 phishscore=0 clxscore=1011 mlxscore=0 spamscore=0 suspectscore=0 malwarescore=0 adultscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408290069 This Series adds support to share QUP based I2C SE between subsystems. Each subsystem should have its own GPII which interacts between SE and GSI DMA HW engine. Subsystem must acquire Lock over the SE on GPII channel so that it gets uninterrupted control till it unlocks the SE. It also makes sure the commonly shared TLMM GPIOs are not touched which can impact other subsystem or cause any interruption. Generally, GPIOs are being unconfigured during suspend time. GSI DMA engine is capable to perform requested transfer operations from any of the SE in a seamless way and its transparent to the subsystems. Make sure to enable “qcom,shared-se” flag only while enabling this feature. I2C client should add in its respective parent node. --- Mukesh Kumar Savaliya (4): dt-bindindgs: i2c: qcom,i2c-geni: Document shared flag dma: gpi: Add Lock and Unlock TRE support to access SE exclusively soc: qcom: geni-se: Export function geni_se_clks_off() i2c: i2c-qcom-geni: Enable i2c controller sharing between two subsystems .../bindings/i2c/qcom,i2c-geni-qcom.yaml | 4 ++ drivers/dma/qcom/gpi.c | 37 ++++++++++++++++++- drivers/i2c/busses/i2c-qcom-geni.c | 29 +++++++++++---- drivers/soc/qcom/qcom-geni-se.c | 4 +- include/linux/dma/qcom-gpi-dma.h | 6 +++ include/linux/soc/qcom/geni-se.h | 3 ++ 6 files changed, 74 insertions(+), 9 deletions(-)