Message ID | 1389852653-8806-1-git-send-email-hongbo.zhang@freescale.com (mailing list archive) |
---|---|
State | Accepted |
Commit | 0ca583a239a8 |
Delegated to: | Vinod Koul |
Headers | show |
On Thu, Jan 16, 2014 at 02:10:53PM +0800, hongbo.zhang@freescale.com wrote: > From: Hongbo Zhang <hongbo.zhang@freescale.com> > > Freescale DMA has a feature of BandWidth Control (ab. BWC), which is currently > 256 bytes and should be changed to 1024 bytes for best DMA throughput. > Changing BWC from 256 to 1024 will improve DMA performance much, in cases > whatever one channel is running or multi channels are running simultanously, > large or small buffers are copied. And this change doesn't impact memory > access performance remarkably, lmbench tests show that for some cases the > memory performance are decreased very slightly, while the others are even > better. > Tested on T4240. Applied, thanks -- ~Vinod -- To unsubscribe from this list: send the line "unsubscribe dmaengine" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h index 1ffc244..d56e835 100644 --- a/drivers/dma/fsldma.h +++ b/drivers/dma/fsldma.h @@ -41,7 +41,7 @@ * channel is allowed to transfer before the DMA engine pauses * the current channel and switches to the next channel */ -#define FSL_DMA_MR_BWC 0x08000000 +#define FSL_DMA_MR_BWC 0x0A000000 /* Special MR definition for MPC8349 */ #define FSL_DMA_MR_EOTIE 0x00000080