From patchwork Mon Jul 14 07:20:01 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xuelin Shi X-Patchwork-Id: 4543271 X-Patchwork-Delegate: dan.j.williams@gmail.com Return-Path: X-Original-To: patchwork-dmaengine@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id BC308C0514 for ; Mon, 14 Jul 2014 08:06:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CB1FA20172 for ; Mon, 14 Jul 2014 08:06:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D033220158 for ; Mon, 14 Jul 2014 08:06:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753220AbaGNIG2 (ORCPT ); Mon, 14 Jul 2014 04:06:28 -0400 Received: from mail-by2lp0243.outbound.protection.outlook.com ([207.46.163.243]:42167 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750943AbaGNIGT (ORCPT ); Mon, 14 Jul 2014 04:06:19 -0400 Received: from BN3PR0301CA0069.namprd03.prod.outlook.com (25.160.152.165) by BLUPR03MB152.namprd03.prod.outlook.com (10.255.212.28) with Microsoft SMTP Server (TLS) id 15.0.985.8; Mon, 14 Jul 2014 08:06:16 +0000 Received: from BN1AFFO11FD051.protection.gbl (2a01:111:f400:7c10::126) by BN3PR0301CA0069.outlook.office365.com (2a01:111:e400:401e::37) with Microsoft SMTP Server (TLS) id 15.0.985.8 via Frontend Transport; Mon, 14 Jul 2014 08:06:16 +0000 Received: from az84smr01.freescale.net (192.88.158.2) by BN1AFFO11FD051.mail.protection.outlook.com (10.58.53.66) with Microsoft SMTP Server (TLS) id 15.0.980.11 via Frontend Transport; Mon, 14 Jul 2014 08:06:16 +0000 Received: from localhost (rock.ap.freescale.net [10.193.20.106]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s6E868Jl027533; Mon, 14 Jul 2014 01:06:11 -0700 From: To: , CC: , , Xuelin Shi , Xuelin Shi Subject: [PATCH] dmaengine: fsl raid parity continuation support Date: Mon, 14 Jul 2014 15:20:01 +0800 Message-ID: <1405322401-20156-1-git-send-email-xuelin.shi@freescale.com> X-Mailer: git-send-email 1.8.4 X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(979002)(6009001)(199002)(189002)(107046002)(48376002)(80022001)(92566001)(83072002)(50466002)(89996001)(62966002)(104016003)(229853001)(106466001)(81156004)(79102001)(77982001)(46102001)(74662001)(31966008)(76482001)(74502001)(85852003)(92726001)(84676001)(50986999)(68736004)(69596002)(83322001)(104166001)(36756003)(19580405001)(97736001)(33646001)(77156001)(99396002)(81342001)(4396001)(21056001)(19580395003)(50226001)(88136002)(86152002)(86362001)(81542001)(57986006)(76506005)(26826002)(85306003)(44976005)(102836001)(6806004)(105606002)(93916002)(87936001)(87286001)(47776003)(20776003)(95666004)(64706001)(969003)(989001)(999001)(1009001)(1019001); DIR:OUT; SFP:; SCL:1; SRVR:BLUPR03MB152; H:az84smr01.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; MX:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: BCL:0;PCL:0;RULEID: X-Forefront-PRVS: 02723F29C4 Received-SPF: Fail (: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=xuelin.shi@freescale.com; X-OriginatorOrg: freescale.com Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Xuelin Shi support more than 16 disks parity computation. Signed-off-by: Xuelin Shi --- comment: passed the raid6 recovery test. drivers/dma/fsl_raid.c | 32 +++++++++++++++++++++++++++++--- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/drivers/dma/fsl_raid.c b/drivers/dma/fsl_raid.c index 1dc5981..935d05a 100644 --- a/drivers/dma/fsl_raid.c +++ b/drivers/dma/fsl_raid.c @@ -328,6 +328,8 @@ static struct dma_async_tx_descriptor *re_jr_prep_genq( struct cmpnd_frame *cf; u32 cdb; unsigned int i, j; + unsigned int save_src_cnt = src_cnt; + int cont_q = 0; if (len > MAX_DATA_LENGTH) { pr_err("Length greater than %d not supported\n", @@ -340,6 +342,11 @@ static struct dma_async_tx_descriptor *re_jr_prep_genq( if (desc <= 0) return NULL; + if (scf && (flags & DMA_PREP_CONTINUE)) { + cont_q = 1; + src_cnt += 1; + } + /* Filling xor CDB */ cdb = RE_XOR_OPCODE << RE_CDB_OPCODE_SHIFT; cdb |= (src_cnt - 1) << RE_CDB_NRCS_SHIFT; @@ -351,8 +358,10 @@ static struct dma_async_tx_descriptor *re_jr_prep_genq( if (scf != NULL) { /* compute q = src0*coef0^src1*coef1^..., * is GF(8) mult */ - for (i = 0; i < src_cnt; i++) + for (i = 0; i < save_src_cnt; i++) xor->gfm[i] = scf[i]; + if (cont_q) + xor->gfm[i++] = 1; } else { /* compute P, that is XOR all srcs */ for (i = 0; i < src_cnt; i++) @@ -367,9 +376,12 @@ static struct dma_async_tx_descriptor *re_jr_prep_genq( fill_cfd_frame(cf, 1, len, dest, 0); /* Fill CFD's rest of the frames with source buffers */ - for (i = 2, j = 0; j < src_cnt; i++, j++) + for (i = 2, j = 0; j < save_src_cnt; i++, j++) fill_cfd_frame(cf, i, len, src[j], 0); + if (cont_q) + fill_cfd_frame(cf, i++, len, dest, 0); + /* Setting the final bit in the last source buffer frame in CFD */ cf[i - 1].efrl32 |= 1 << CF_FINAL_SHIFT; @@ -404,6 +416,7 @@ static struct dma_async_tx_descriptor *re_jr_prep_pq( u32 cdb; u8 *p; int gfmq_len, i, j; + unsigned long save_src_cnt = src_cnt; if (len > MAX_DATA_LENGTH) { pr_err("Length greater than %d not supported\n", @@ -445,6 +458,9 @@ static struct dma_async_tx_descriptor *re_jr_prep_pq( return re_jr_prep_genq(chan, dest[1], src, src_cnt, scf, len, flags); + if (flags & DMA_PREP_CONTINUE) + src_cnt += 3; + jr = container_of(chan, struct re_jr, chan); desc = re_jr_alloc_desc(jr, flags); if (desc <= 0) @@ -482,9 +498,19 @@ static struct dma_async_tx_descriptor *re_jr_prep_pq( fill_cfd_frame(cf, i, len, dest[j], 0); /* Fill CFD's rest of the frames with source buffers */ - for (i = 3, j = 0; j < src_cnt; i++, j++) + for (i = 3, j = 0; j < save_src_cnt; i++, j++) fill_cfd_frame(cf, i, len, src[j], 0); + /* PQ computation continuation */ + if (src_cnt - save_src_cnt == 3) { + p[save_src_cnt] = 0; + p[save_src_cnt + 1] = 0; + p[save_src_cnt + 2] = 1; + fill_cfd_frame(cf, i++, len, dest[0], 0); + fill_cfd_frame(cf, i++, len, dest[1], 0); + fill_cfd_frame(cf, i++, len, dest[1], 0); + } + /* Setting the final bit in the last source buffer frame in CFD */ cf[i - 1].efrl32 |= 1 << CF_FINAL_SHIFT;