From patchwork Mon Jul 28 12:17:48 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srikanth Thokala X-Patchwork-Id: 4633651 Return-Path: X-Original-To: patchwork-dmaengine@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E31269F36A for ; Mon, 28 Jul 2014 12:18:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 13B9F2018B for ; Mon, 28 Jul 2014 12:18:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 38EB52018E for ; Mon, 28 Jul 2014 12:18:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752242AbaG1MSN (ORCPT ); Mon, 28 Jul 2014 08:18:13 -0400 Received: from mail-yk0-f169.google.com ([209.85.160.169]:58367 "EHLO mail-yk0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751598AbaG1MSM (ORCPT ); Mon, 28 Jul 2014 08:18:12 -0400 Received: by mail-yk0-f169.google.com with SMTP id 131so4630262ykp.0 for ; Mon, 28 Jul 2014 05:18:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id; bh=/JtybiwtfvNOtfASg3aOFicEitHeVjXFy0jwDyyOheI=; b=hciBTUSdCS0fospSy6TXQUojRqcZ8sewaDE2ryUejP/dSCeDTRjmHIkDD817pwq8US KBYyE2s6IeVQwJVk5caUN4UWAk9pTQc3ClqnXcZsgOmo9g+G8JznWBxgZE0mDe/5kwFW Qxkm2Ep7Vd9kyLwuphUhg4uxE95ysYNEcQVtJiYBu2r70bQGID+HTxiwqPiAeSuhtzoc MzhHTnVVzIeaJIM2qkkQvPetLVR4AIlGV1GwnwpYWLQ3kO3H0u1VsWuA8E0q4J3ufo2a VWobmOj4V3ZNezCNYBadyMMn1nuRQ5/i35eqlhpLTcjv4TOAnV5qeslhds8Cb3NEqt6s I6bw== X-Received: by 10.236.112.167 with SMTP id y27mr49785321yhg.60.1406549891947; Mon, 28 Jul 2014 05:18:11 -0700 (PDT) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPSA id d46sm37460052yha.10.2014.07.28.05.18.09 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 28 Jul 2014 05:18:10 -0700 (PDT) From: Srikanth Thokala To: vinod.koul@intel.com, dan.j.williams@intel.com, michal.simek@xilinx.com, grant.likely@linaro.org, robh+dt@kernel.org, levex@linux.com, jassisinghbrar@gmail.com Cc: linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, anirudh@xilinx.com, svemula@xilinx.com, Srikanth Thokala Subject: [PATCH v3 1/2] dma: Add Xilinx AXI DMA DT Binding Documentation Date: Mon, 28 Jul 2014 17:47:48 +0530 Message-Id: <1406549869-24422-1-git-send-email-sthokal@xilinx.com> X-Mailer: git-send-email 1.7.9.5 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Device-tree binding documentation of Xilinx DMA Engine Signed-off-by: Srikanth Thokala Acked-by: Arnd Bergmann --- Changes in v3: - Change property 'xlnx,data-width' to 'xlnx,datawidth' in the description to match the implementation. Changes in v2: None --- .../devicetree/bindings/dma/xilinx/xilinx_dma.txt | 65 ++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt new file mode 100644 index 0000000..18e8bcc --- /dev/null +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt @@ -0,0 +1,65 @@ +Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream +target devices. It can be configured to have one channel or two channels. +If configured as two channels, one is to transmit to the device and another +is to receive from the device. + +Required properties: +- compatible: Should be "xlnx,axi-dma-1.00.a" +- #dma-cells: Should be <1>, see "dmas" property below +- reg: Should contain DMA registers location and length. +- dma-channel child node: Should have atleast one channel and can have upto + two channels per device. This node specifies the properties of each + DMA channel (see child node properties below). + +Optional properties: +- xlnx,include-sg: Tells whether configured for Scatter-mode in + the hardware. + +Required child node properties: +- compatible: It should be either "xlnx,axi-dma-mm2s-channel" or + "xlnx,axi-dma-s2mm-channel". +- interrupts: Should contain per channel DMA interrupts. +- xlnx,datawidth: Should contain the stream data width, take values + {32,64...1024}. + +Option child node properties: +- xlnx,include-dre: Tells whether hardware is configured for Data + Realignment Engine. + +Example: +++++++++ + +axi_dma_0: axidma@40400000 { + compatible = "xlnx,axi-dma-1.00.a"; + #dma_cells = <1>; + reg = < 0x40400000 0x10000 >; + dma-channel@40400000 { + compatible = "xlnx,axi-dma-mm2s-channel"; + interrupts = < 0 59 4 >; + xlnx,datawidth = <0x40>; + } ; + dma-channel@40400030 { + compatible = "xlnx,axi-dma-s2mm-channel"; + interrupts = < 0 58 4 >; + xlnx,datawidth = <0x40>; + } ; +} ; + + +* DMA client + +Required properties: +- dmas: a list of <[DMA device phandle] [Channel ID]> pairs, + where Channel ID is '0' for write/tx and '1' for read/rx + channel. +- dma-names: a list of DMA channel names, one per "dmas" entry + +Example: +++++++++ + +dmatest_0: dmatest@0 { + compatible ="xlnx,axi-dma-test-1.00.a"; + dmas = <&axi_dma_0 0 + &axi_dma_0 1>; + dma-names = "dma0", "dma1"; +} ;