From patchwork Mon Nov 17 13:42:25 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 5320421 Return-Path: X-Original-To: patchwork-dmaengine@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 6C6339F1E1 for ; Mon, 17 Nov 2014 13:57:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 832B62011E for ; Mon, 17 Nov 2014 13:57:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 862BE2010F for ; Mon, 17 Nov 2014 13:57:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753294AbaKQNp2 (ORCPT ); Mon, 17 Nov 2014 08:45:28 -0500 Received: from down.free-electrons.com ([37.187.137.238]:48964 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753284AbaKQNpZ (ORCPT ); Mon, 17 Nov 2014 08:45:25 -0500 Received: by mail.free-electrons.com (Postfix, from userid 106) id 66243774; Mon, 17 Nov 2014 14:45:31 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost (col31-4-88-188-83-94.fbx.proxad.net [88.188.83.94]) by mail.free-electrons.com (Postfix) with ESMTPSA id 02CC3746; Mon, 17 Nov 2014 14:45:30 +0100 (CET) From: Maxime Ripard To: Vinod Koul , dmaengine@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Laurent Pinchart , =?UTF-8?q?Antoine=20T=C3=A9nart?= , Russell King , lars@metafoo.de, Maxime Ripard Subject: [PATCH v5 31/61] dmaengine: mpc512x: Split device_control Date: Mon, 17 Nov 2014 14:42:25 +0100 Message-Id: <1416231775-31252-32-git-send-email-maxime.ripard@free-electrons.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1416231775-31252-1-git-send-email-maxime.ripard@free-electrons.com> References: <1416231775-31252-1-git-send-email-maxime.ripard@free-electrons.com> Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Split the device_control callback of the Freescale MPC512x DMA driver to make use of the newly introduced callbacks, that will eventually be used to retrieve slave capabilities. Signed-off-by: Maxime Ripard --- drivers/dma/mpc512x_dma.c | 111 +++++++++++++++++++++------------------------- 1 file changed, 51 insertions(+), 60 deletions(-) diff --git a/drivers/dma/mpc512x_dma.c b/drivers/dma/mpc512x_dma.c index 01bec4023de2..57d2457545f3 100644 --- a/drivers/dma/mpc512x_dma.c +++ b/drivers/dma/mpc512x_dma.c @@ -800,79 +800,69 @@ err_prep: return NULL; } -static int mpc_dma_device_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, - unsigned long arg) +static int mpc_dma_device_config(struct dma_chan *chan, + struct dma_slave_config *cfg) { - struct mpc_dma_chan *mchan; - struct mpc_dma *mdma; - struct dma_slave_config *cfg; + struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan); unsigned long flags; - mchan = dma_chan_to_mpc_dma_chan(chan); - switch (cmd) { - case DMA_TERMINATE_ALL: - /* Disable channel requests */ - mdma = dma_chan_to_mpc_dma(chan); - - spin_lock_irqsave(&mchan->lock, flags); - - out_8(&mdma->regs->dmacerq, chan->chan_id); - list_splice_tail_init(&mchan->prepared, &mchan->free); - list_splice_tail_init(&mchan->queued, &mchan->free); - list_splice_tail_init(&mchan->active, &mchan->free); - - spin_unlock_irqrestore(&mchan->lock, flags); + /* + * Software constraints: + * - only transfers between a peripheral device and + * memory are supported; + * - only peripheral devices with 4-byte FIFO access register + * are supported; + * - minimal transfer chunk is 4 bytes and consequently + * source and destination addresses must be 4-byte aligned + * and transfer size must be aligned on (4 * maxburst) + * boundary; + * - during the transfer RAM address is being incremented by + * the size of minimal transfer chunk; + * - peripheral port's address is constant during the transfer. + */ - return 0; + if (cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES || + cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES || + !IS_ALIGNED(cfg->src_addr, 4) || + !IS_ALIGNED(cfg->dst_addr, 4)) { + return -EINVAL; + } - case DMA_SLAVE_CONFIG: - /* - * Software constraints: - * - only transfers between a peripheral device and - * memory are supported; - * - only peripheral devices with 4-byte FIFO access register - * are supported; - * - minimal transfer chunk is 4 bytes and consequently - * source and destination addresses must be 4-byte aligned - * and transfer size must be aligned on (4 * maxburst) - * boundary; - * - during the transfer RAM address is being incremented by - * the size of minimal transfer chunk; - * - peripheral port's address is constant during the transfer. - */ + spin_lock_irqsave(&mchan->lock, flags); - cfg = (void *)arg; + mchan->src_per_paddr = cfg->src_addr; + mchan->src_tcd_nunits = cfg->src_maxburst; + mchan->dst_per_paddr = cfg->dst_addr; + mchan->dst_tcd_nunits = cfg->dst_maxburst; - if (cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES || - cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES || - !IS_ALIGNED(cfg->src_addr, 4) || - !IS_ALIGNED(cfg->dst_addr, 4)) { - return -EINVAL; - } + /* Apply defaults */ + if (mchan->src_tcd_nunits == 0) + mchan->src_tcd_nunits = 1; + if (mchan->dst_tcd_nunits == 0) + mchan->dst_tcd_nunits = 1; - spin_lock_irqsave(&mchan->lock, flags); + spin_unlock_irqrestore(&mchan->lock, flags); - mchan->src_per_paddr = cfg->src_addr; - mchan->src_tcd_nunits = cfg->src_maxburst; - mchan->dst_per_paddr = cfg->dst_addr; - mchan->dst_tcd_nunits = cfg->dst_maxburst; + return 0; +} - /* Apply defaults */ - if (mchan->src_tcd_nunits == 0) - mchan->src_tcd_nunits = 1; - if (mchan->dst_tcd_nunits == 0) - mchan->dst_tcd_nunits = 1; +static int mpc_dma_device_terminate_all(struct dma_chan *chan) +{ + struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan); + struct mpc_dma *mdma = dma_chan_to_mpc_dma(chan); + unsigned long flags; - spin_unlock_irqrestore(&mchan->lock, flags); + /* Disable channel requests */ + spin_lock_irqsave(&mchan->lock, flags); - return 0; + out_8(&mdma->regs->dmacerq, chan->chan_id); + list_splice_tail_init(&mchan->prepared, &mchan->free); + list_splice_tail_init(&mchan->queued, &mchan->free); + list_splice_tail_init(&mchan->active, &mchan->free); - default: - /* Unknown command */ - break; - } + spin_unlock_irqrestore(&mchan->lock, flags); - return -ENXIO; + return 0; } static int mpc_dma_probe(struct platform_device *op) @@ -963,7 +953,8 @@ static int mpc_dma_probe(struct platform_device *op) dma->device_tx_status = mpc_dma_tx_status; dma->device_prep_dma_memcpy = mpc_dma_prep_memcpy; dma->device_prep_slave_sg = mpc_dma_prep_slave_sg; - dma->device_control = mpc_dma_device_control; + dma->device_config = mpc_dma_device_config; + dma->device_terminate_all = mpc_dma_device_terminate_all; INIT_LIST_HEAD(&dma->channels); dma_cap_set(DMA_MEMCPY, dma->cap_mask);