From patchwork Thu Jul 9 03:25:45 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sricharan Ramabadhran X-Patchwork-Id: 6752761 Return-Path: X-Original-To: patchwork-dmaengine@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B8CAF9F319 for ; Thu, 9 Jul 2015 03:27:53 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B9A6120562 for ; Thu, 9 Jul 2015 03:27:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9F77120665 for ; Thu, 9 Jul 2015 03:27:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753349AbbGID0P (ORCPT ); Wed, 8 Jul 2015 23:26:15 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:41802 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753313AbbGID0L (ORCPT ); Wed, 8 Jul 2015 23:26:11 -0400 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 94ADA140D70; Thu, 9 Jul 2015 03:26:10 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id 84850140D78; Thu, 9 Jul 2015 03:26:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from blr-ubuntu-32.ap.qualcomm.com (unknown [202.46.23.61]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: sricharan@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 64815140D74; Thu, 9 Jul 2015 03:26:06 +0000 (UTC) From: Sricharan R To: iivanov@mm-sol.com, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, galak@codeaurora.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, agross@codeaurora.org, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: sricharan@codeaurora.org Subject: [PATCH V4 2/7] qup: i2c: factor out common code for reuse Date: Thu, 9 Jul 2015 08:55:45 +0530 Message-Id: <1436412350-19519-3-git-send-email-sricharan@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1436412350-19519-1-git-send-email-sricharan@codeaurora.org> References: <1436412350-19519-1-git-send-email-sricharan@codeaurora.org> X-Virus-Scanned: ClamAV using ClamSMTP Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The qup_i2c_write/read_one functions can be split to have the common initialization code and function to loop around the data bytes separately. This way the initialization code can be reused while adding v2 tags functionality. Signed-off-by: Sricharan R --- drivers/i2c/busses/i2c-qup.c | 147 +++++++++++++++++++++++++------------------ 1 file changed, 87 insertions(+), 60 deletions(-) diff --git a/drivers/i2c/busses/i2c-qup.c b/drivers/i2c/busses/i2c-qup.c index 81ed120..131dc28 100644 --- a/drivers/i2c/busses/i2c-qup.c +++ b/drivers/i2c/busses/i2c-qup.c @@ -324,53 +324,72 @@ static int qup_i2c_issue_write(struct qup_i2c_dev *qup, struct i2c_msg *msg) return ret; } -static int qup_i2c_write_one(struct qup_i2c_dev *qup, struct i2c_msg *msg) +static int qup_i2c_wait_for_complete(struct qup_i2c_dev *qup, + struct i2c_msg *msg) { unsigned long left; - int ret; - - qup->msg = msg; - qup->pos = 0; + int ret = 0; - enable_irq(qup->irq); + left = wait_for_completion_timeout(&qup->xfer, HZ); + if (!left) { + writel(1, qup->base + QUP_SW_RESET); + ret = -ETIMEDOUT; + } - qup_i2c_set_write_mode(qup, msg); + if (qup->bus_err || qup->qup_err) { + if (qup->bus_err & QUP_I2C_NACK_FLAG) { + dev_err(qup->dev, "NACK from %x\n", msg->addr); + ret = -EIO; + } + } - ret = qup_i2c_change_state(qup, QUP_RUN_STATE); - if (ret) - goto err; + return ret; +} - writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); +static int qup_i2c_write_one(struct qup_i2c_dev *qup, struct i2c_msg *msg) +{ + int ret = 0; do { ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE); if (ret) - goto err; + return ret; ret = qup_i2c_issue_write(qup, msg); if (ret) - goto err; + return ret; ret = qup_i2c_change_state(qup, QUP_RUN_STATE); if (ret) - goto err; - - left = wait_for_completion_timeout(&qup->xfer, HZ); - if (!left) { - writel(1, qup->base + QUP_SW_RESET); - ret = -ETIMEDOUT; - goto err; - } + return ret; - if (qup->bus_err || qup->qup_err) { - if (qup->bus_err & QUP_I2C_NACK_FLAG) - dev_err(qup->dev, "NACK from %x\n", msg->addr); - ret = -EIO; - goto err; - } + ret = qup_i2c_wait_for_complete(qup, msg); + if (ret) + return ret; } while (qup->pos < msg->len); - /* Wait for the outstanding data in the fifo to drain */ + return ret; +} + +static int qup_i2c_write(struct qup_i2c_dev *qup, struct i2c_msg *msg) +{ + int ret; + + qup->msg = msg; + qup->pos = 0; + enable_irq(qup->irq); + qup_i2c_set_write_mode(qup, msg); + + ret = qup_i2c_change_state(qup, QUP_RUN_STATE); + if (ret) + goto err; + + writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); + + ret = qup_i2c_write_one(qup, msg); + if (ret) + goto err; + ret = qup_i2c_wait_ready(qup, QUP_OUT_NOT_EMPTY, RESET_BIT, ONE_BYTE); err: @@ -436,51 +455,59 @@ static int qup_i2c_read_fifo(struct qup_i2c_dev *qup, struct i2c_msg *msg) static int qup_i2c_read_one(struct qup_i2c_dev *qup, struct i2c_msg *msg) { - unsigned long left; - int ret; + int ret = 0; - qup->msg = msg; - qup->pos = 0; + /* + * The QUP block will issue a NACK and STOP on the bus when reaching + * the end of the read, the length of the read is specified as one byte + * which limits the possible read to 256 (QUP_READ_LIMIT) bytes. + */ + if (msg->len > QUP_READ_LIMIT) { + dev_err(qup->dev, "HW not capable of reads over %d bytes\n", + QUP_READ_LIMIT); + return -EINVAL; + } - enable_irq(qup->irq); + ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE); + if (ret) + return ret; - qup_i2c_set_read_mode(qup, msg->len); + qup_i2c_issue_read(qup, msg); ret = qup_i2c_change_state(qup, QUP_RUN_STATE); if (ret) - goto err; + return ret; - writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); + do { + ret = qup_i2c_wait_for_complete(qup, msg); + if (ret) + return ret; + ret = qup_i2c_read_fifo(qup, msg); + if (ret) + return ret; + } while (qup->pos < msg->len); - ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE); - if (ret) - goto err; + return ret; +} - qup_i2c_issue_read(qup, msg); +static int qup_i2c_read(struct qup_i2c_dev *qup, struct i2c_msg *msg) +{ + int ret; + + qup->msg = msg; + qup->pos = 0; + + enable_irq(qup->irq); + + qup_i2c_set_read_mode(qup, msg->len); ret = qup_i2c_change_state(qup, QUP_RUN_STATE); if (ret) goto err; - do { - left = wait_for_completion_timeout(&qup->xfer, HZ); - if (!left) { - writel(1, qup->base + QUP_SW_RESET); - ret = -ETIMEDOUT; - goto err; - } - - if (qup->bus_err || qup->qup_err) { - if (qup->bus_err & QUP_I2C_NACK_FLAG) - dev_err(qup->dev, "NACK from %x\n", msg->addr); - ret = -EIO; - goto err; - } + writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); - ret = qup_i2c_read_fifo(qup, msg); - if (ret) - goto err; - } while (qup->pos < msg->len); + ret = qup_i2c_read_one(qup, msg); err: disable_irq(qup->irq); @@ -520,9 +547,9 @@ static int qup_i2c_xfer(struct i2c_adapter *adap, } if (msgs[idx].flags & I2C_M_RD) - ret = qup_i2c_read_one(qup, &msgs[idx]); + ret = qup_i2c_read(qup, &msgs[idx]); else - ret = qup_i2c_write_one(qup, &msgs[idx]); + ret = qup_i2c_write(qup, &msgs[idx]); if (ret) break;