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Wed, 15 Jul 2015 09:37:49 +0000 Received: from titan.ap.freescale.net ([10.192.208.233]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id t6F9bgoG014065; Wed, 15 Jul 2015 02:37:46 -0700 From: Yuan Yao To: , CC: , , , Subject: [PATCH] dmaengine: fsl-edma: add PM suspend/resume support Date: Wed, 15 Jul 2015 17:32:58 +0800 Message-ID: <1436952778-28000-2-git-send-email-yao.yuan@freescale.com> X-Mailer: git-send-email 2.1.0.27.g96db324 In-Reply-To: <1436952778-28000-1-git-send-email-yao.yuan@freescale.com> References: <1436952778-28000-1-git-send-email-yao.yuan@freescale.com> X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1; BN1BFFO11FD001; 1:AwmeSNtOmYc0pvcwd1vJV2FXv7DKL+5iAPFc0q4oTKQh/OQdHweeiDq2lwnCQGJIW/QJlc/nSDmyRDxSrq2f1dT9GpsvwwA3IN1eSuTzbQ/FXkHbWmAui7mtCm8IUkW33nLb1T5JYDI6jaZRxfi2dAc4k12ovrzMT+TrP5ryaL38OUqtcg0AuoTuAfSQzBY9DxpSLQHKsPJ4r16OEw/IVPCrZ4tFgzRdFXmGrhQgdh05LAmZ9j5QoGS/CqWcAtlvZgKGSq2xdailDf4Cm/jmgG08CQnlmMqAudt86sLgrRw6epKAqSJZCFzzYhrQBTPvQLH2pmO9U++AR/fzW/o2YF5Deu2SXMIjxHV8pgLNdaF56cb+c2L8A7V/3a1sRLol2DNKXgfgfIy4Bs8bdG7HHDSaUqhqBrpkAtXAqd6Hxw/Hx+/hTPYzUJgPnDB2mYMm X-Forefront-Antispam-Report: CIP:192.88.158.2; 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BLUPR03MB603; 23:LYXs/ox6JB4yCsinraC7u7hlv5HIYXtPannGjTQoVDks8iYfq51ww66HSV/2v9lffVwrXPSz5Q6BhBMnh6sCfB2ANBKWWsEHlMSd6ToOyMXUfkteYutW0nBQ2c6J7nUxA2s+9r3WwEvBqO9fkZXbhvhyfEGuZR0J8pBpaQZJyS7jEvtByQ2Iu3HzBsw6hm8DumLb6RjlzdcfJl7BJiYDo7sdK7kMuKinH9T/A/93uGDv5fMqNpYdsL4ZTZHieXRZfOlgn3gZnbjO9/9Iorfw0EXbubBQREYpfTyA8Lcbrf45uSnVu2w1XELiwPfPLc6/S/QKDN2Ff/pFPWz8DHBpJ9qz4kLC8N98sCQ6MfYlmgKB3Ep2KDLb8Mq9aM4jyk7XJR2QNMyGXYS6Oohmg6FlhqKuCGo8rVa7l8YnB4kH+Xxc2kF/5Ws5n3dXP8weD2qpYc7+y9ERQUm4PdmTwl/A/hhflALH9ibDC1DSx+tq8odwor2j22/HQo5dj3S3q463ll69J9xaDwaCD1apg/9y1d1/57mV5e8t6u6gZkXoEnF5kDashMlf1Q2HwZFtWeEJItk9eAAhhLXdTqujSRDQeVDtYy+gszoJ/SYSMNHxBXLGIBUcHrGLhbu01u7dyFIeRfpdMg4bbWKfrxLn8drWHOb6zSnT1GbljO9Um1HC/8R0PCiN1AcH0R5gr+FwPC4K1n/LKBJiroilO9PpD5cB03Mu6CfiIlzCzUMyrESUyjlJgYWPZgyVpGMAH0o1QESYwEgNOv+zDbTYfVOnkBoPA1qA2bA4XDEKNbp4kjJ2OEh0Ls5tupa1ymqj/EI5P9vSMy+KYozwpA3XjFV9vEvMsNAR+zySk/C64nV10HsQpaXsn3F3Id2Gi7In1emZ93hIvoj6MLV3sGpSYdV6WOh/jQ== X-Microsoft-Exchange-Diagnostics: 1; BLUPR03MB603; 5:/YtRTZaULLIDpcc/m9Yxqr4HKTlDYliDg8CcmStZGilQ+ZEfKHds9gwfkbjVvndqvHXjcebCK/q+w6Ctj/81yooEzr/SzvsMeA5uMztpwPKPvVOOoOwZK4kRJpFWhiPNGsDajvbtMnOOztkK2sG51A==; 24:7mvi/+lr6RJKGtvv/X4FDe7xkVWS2ylys33LYGZnbz1QYOYegCNsWJIzALJIdhbi/x7q/i5jQqy5kQVq4QsLlLskytjfMb2pMlhEBD/ZyT8=; 20:njEYgWo+LRqaQ2kmBy8c39QybgG2LwLTorpUR6GJiD3UfHx1+zw6Xun0eQMj1zb/oB4Uqbyyo9OdG3+tKjrJCg== X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2015 09:37:49.5064 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.158.2]; Helo=[az84smr01.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR03MB603 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This add power management suspend/resume support for the fsl-edma driver. eDMA acted as a basic function used by others. What it needs to do is the two steps below to support power management. In fsl_edma_suspend_late: Check whether the DMA chan is idle and if it is not idle, stop PM operation. In fsl_edma_resume_early: Enable the eDMA and wait for being used. Signed-off-by: Yuan Yao --- drivers/dma/fsl-edma.c | 92 +++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 91 insertions(+), 1 deletion(-) diff --git a/drivers/dma/fsl-edma.c b/drivers/dma/fsl-edma.c index 915eec3..f987a4f 100644 --- a/drivers/dma/fsl-edma.c +++ b/drivers/dma/fsl-edma.c @@ -116,6 +116,12 @@ BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) +#ifdef CONFIG_PM +enum fsl_edma_pm_state { + RUNNING = 0, + SUSPENDED, +}; +#endif struct fsl_edma_hw_tcd { __le32 saddr; @@ -151,6 +157,11 @@ struct fsl_edma_chan { struct fsl_edma_desc *edesc; struct fsl_edma_slave_config fsc; struct dma_pool *tcd_pool; + bool idle; +#ifdef CONFIG_PM + u32 slave_id; + enum fsl_edma_pm_state pm_state; +#endif }; struct fsl_edma_desc { @@ -298,6 +309,7 @@ static int fsl_edma_terminate_all(struct dma_chan *chan) spin_lock_irqsave(&fsl_chan->vchan.lock, flags); fsl_edma_disable_request(fsl_chan); fsl_chan->edesc = NULL; + fsl_chan->idle = true; vchan_get_all_descriptors(&fsl_chan->vchan, &head); spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); vchan_dma_desc_free_list(&fsl_chan->vchan, &head); @@ -313,6 +325,7 @@ static int fsl_edma_pause(struct dma_chan *chan) if (fsl_chan->edesc) { fsl_edma_disable_request(fsl_chan); fsl_chan->status = DMA_PAUSED; + fsl_chan->idle = true; } spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); return 0; @@ -327,6 +340,7 @@ static int fsl_edma_resume(struct dma_chan *chan) if (fsl_chan->edesc) { fsl_edma_enable_request(fsl_chan); fsl_chan->status = DMA_IN_PROGRESS; + fsl_chan->idle = false; } spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); return 0; @@ -648,6 +662,7 @@ static void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan) fsl_edma_set_tcd_regs(fsl_chan, fsl_chan->edesc->tcd[0].vtcd); fsl_edma_enable_request(fsl_chan); fsl_chan->status = DMA_IN_PROGRESS; + fsl_chan->idle = false; } static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id) @@ -676,6 +691,7 @@ static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id) vchan_cookie_complete(&fsl_chan->edesc->vdesc); fsl_chan->edesc = NULL; fsl_chan->status = DMA_COMPLETE; + fsl_chan->idle = true; } else { vchan_cyclic_callback(&fsl_chan->edesc->vdesc); } @@ -704,6 +720,7 @@ static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id) edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), fsl_edma->membase + EDMA_CERR); fsl_edma->chans[ch].status = DMA_ERROR; + fsl_edma->chans[ch].idle = true; } } return IRQ_HANDLED; @@ -724,6 +741,14 @@ static void fsl_edma_issue_pending(struct dma_chan *chan) spin_lock_irqsave(&fsl_chan->vchan.lock, flags); +#ifdef CONFIG_PM + if (unlikely(fsl_chan->pm_state != RUNNING)) { + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); + /* cannot submit due to suspend */ + return; + } +#endif + if (vchan_issue_pending(&fsl_chan->vchan) && !fsl_chan->edesc) fsl_edma_xfer_desc(fsl_chan); @@ -750,6 +775,10 @@ static struct dma_chan *fsl_edma_xlate(struct of_phandle_args *dma_spec, chan->device->privatecnt++; fsl_edma_chan_mux(to_fsl_edma_chan(chan), dma_spec->args[1], true); +#ifdef CONFIG_PM + to_fsl_edma_chan(chan)->slave_id = + dma_spec->args[1]; +#endif mutex_unlock(&fsl_edma->fsl_edma_mutex); return chan; } @@ -888,7 +917,11 @@ static int fsl_edma_probe(struct platform_device *pdev) struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i]; fsl_chan->edma = fsl_edma; - +#ifdef CONFIG_PM + fsl_chan->pm_state = RUNNING; + fsl_chan->slave_id = 0; +#endif + fsl_chan->idle = true; fsl_chan->vchan.desc_free = fsl_edma_free_desc; vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev); @@ -959,6 +992,60 @@ static int fsl_edma_remove(struct platform_device *pdev) return 0; } +#ifdef CONFIG_PM +static int fsl_edma_suspend_late(struct device *dev) +{ + struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev); + struct fsl_edma_chan *fsl_chan; + unsigned long flags; + int i; + + for (i = 0; i < fsl_edma->n_chans; i++) { + fsl_chan = &fsl_edma->chans[i]; + spin_lock_irqsave(&fsl_chan->vchan.lock, flags); + /* Make sure chan is idle or can not into suspend. */ + if (unlikely(!fsl_chan->idle)) + goto out; + fsl_chan->pm_state = SUSPENDED; + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); + } + return 0; + +out: + for (; i >= 0; i--) { + fsl_chan = &fsl_edma->chans[i]; + fsl_chan->pm_state = RUNNING; + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); + } + return -EBUSY; +} + +static int fsl_edma_resume_early(struct device *dev) +{ + struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev); + struct fsl_edma_chan *fsl_chan; + int i; + + for (i = 0; i < fsl_edma->n_chans; i++) { + fsl_chan = &fsl_edma->chans[i]; + fsl_chan->pm_state = RUNNING; + edma_writew(fsl_edma, 0x0, fsl_edma->membase + EDMA_TCD_CSR(i)); + if (fsl_chan->slave_id != 0) + fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id, true); + } + + edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, + fsl_edma->membase + EDMA_CR); + + return 0; +} + +static const struct dev_pm_ops fsl_edma_pm_ops = { + .suspend_late = fsl_edma_suspend_late, + .resume_early = fsl_edma_resume_early, +}; +#endif + static const struct of_device_id fsl_edma_dt_ids[] = { { .compatible = "fsl,vf610-edma", }, { /* sentinel */ } @@ -969,6 +1056,9 @@ static struct platform_driver fsl_edma_driver = { .driver = { .name = "fsl-edma", .of_match_table = fsl_edma_dt_ids, +#ifdef CONFIG_PM + .pm = &fsl_edma_pm_ops, +#endif }, .probe = fsl_edma_probe, .remove = fsl_edma_remove,