From patchwork Tue Aug 18 13:49:14 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 7031491 Return-Path: X-Original-To: patchwork-dmaengine@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B04CCC05AC for ; Tue, 18 Aug 2015 13:51:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C6BD1207B6 for ; Tue, 18 Aug 2015 13:51:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CAE35207AF for ; Tue, 18 Aug 2015 13:51:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751056AbbHRNvE (ORCPT ); Tue, 18 Aug 2015 09:51:04 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:10071 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753036AbbHRNuc (ORCPT ); Tue, 18 Aug 2015 09:50:32 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Tue, 18 Aug 2015 06:49:45 -0700 Received: from hqemhub02.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Tue, 18 Aug 2015 06:47:18 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Tue, 18 Aug 2015 06:47:18 -0700 Received: from jonathanh-lm.nvidia.com (172.20.144.16) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server (TLS) id 8.3.342.0; Tue, 18 Aug 2015 06:50:30 -0700 From: Jon Hunter To: Laxman Dewangan , Vinod Koul , Stephen Warren , Thierry Reding , Alexandre Courbot CC: , , , , Jon Hunter , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala Subject: [RFC PATCH 6/7] Documentation: DT: Add binding documentation for NVIDIA ADMA Date: Tue, 18 Aug 2015 14:49:14 +0100 Message-ID: <1439905755-25150-7-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1439905755-25150-1-git-send-email-jonathanh@nvidia.com> References: <1439905755-25150-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add device-tree binding documentation for the Tegra210 Audio DMA controller. Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Signed-off-by: Jon Hunter --- .../devicetree/bindings/dma/tegra210-adma.txt | 49 ++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/tegra210-adma.txt diff --git a/Documentation/devicetree/bindings/dma/tegra210-adma.txt b/Documentation/devicetree/bindings/dma/tegra210-adma.txt new file mode 100644 index 000000000000..38310d7e7e77 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/tegra210-adma.txt @@ -0,0 +1,49 @@ +* NVIDIA Tegra Audio DMA controller + +Required properties: +- compatible: Should be "nvidia,-adma" +- reg: Should contain DMA registers location and length. This should include + all of the per-channel registers. +- interrupt-parent: Phandle to the interrupt parent controller. +- interrupts: Should contain all of the per-channel DMA interrupts. +- clocks: Must contain two entries, one for the power-domain clock and one + for the module clock. + See ../clocks/clock-bindings.txt for details. +- #dma-cells : Must be <1>. This dictates the length of DMA specifiers in + client nodes' dmas properties. The specifier represents the DMA request + select value for the peripheral. For more details, consult the Tegra TRM's + documentation of the APB DMA channel control register REQ_SEL field. + +Examples: + +adma: adma@702e2000 { + compatible = "nvidia,tegra210-adma"; + reg = <0x0 0x702e2000 0x0 0x2000>; + interrupt-parent = <&tegra_agic>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>, + <&tegra_car TEGRA210_CLK_ADMA_APE>; + clock-names = "adma", "adma.ape"; + #dma-cells = <1>; +};