From patchwork Thu Sep 10 08:37:44 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 7152291 Return-Path: X-Original-To: patchwork-dmaengine@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id DF554BEEC1 for ; Thu, 10 Sep 2015 08:42:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1244F20457 for ; Thu, 10 Sep 2015 08:42:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 15B2E2041E for ; Thu, 10 Sep 2015 08:42:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754589AbbIJIjY (ORCPT ); Thu, 10 Sep 2015 04:39:24 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:39838 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753518AbbIJIjN (ORCPT ); Thu, 10 Sep 2015 04:39:13 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id t8A8chaP017122; Thu, 10 Sep 2015 03:38:43 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id t8A8chUD008944; Thu, 10 Sep 2015 03:38:43 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.224.2; Thu, 10 Sep 2015 03:38:34 -0500 Received: from dlep32.itg.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id t8A8bqL4018732; Thu, 10 Sep 2015 03:38:41 -0500 From: Peter Ujfalusi To: , , CC: , , , , , Subject: [PATCH 15/21] dmaengine: edma: Use dev_dbg instead pr_debug Date: Thu, 10 Sep 2015 11:37:44 +0300 Message-ID: <1441874270-2399-16-git-send-email-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.5.1 In-Reply-To: <1441874270-2399-1-git-send-email-peter.ujfalusi@ti.com> References: <1441874270-2399-1-git-send-email-peter.ujfalusi@ti.com> MIME-Version: 1.0 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We have access to dev, so it is better to use the dev_dbg for debug prints. Signed-off-by: Peter Ujfalusi --- drivers/dma/edma.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 71de1c843bb4..5b97c11a33af 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -655,14 +655,14 @@ static int edma_start(struct edma_cc *ecc, unsigned channel) /* EDMA channels without event association */ if (test_bit(channel, ecc->edma_unused)) { - pr_debug("EDMA: ESR%d %08x\n", j, - edma_shadow0_read_array(ecc, SH_ESR, j)); + dev_dbg(ecc->dev, "ESR%d %08x\n", j, + edma_shadow0_read_array(ecc, SH_ESR, j)); edma_shadow0_write_array(ecc, SH_ESR, j, mask); return 0; } /* EDMA channel with event association */ - pr_debug("EDMA: ER%d %08x\n", j, + dev_dbg(ecc->dev, "ER%d %08x\n", j, edma_shadow0_read_array(ecc, SH_ER, j)); /* Clear any pending event or error */ edma_write_array(ecc, EDMA_ECR, j, mask); @@ -670,8 +670,8 @@ static int edma_start(struct edma_cc *ecc, unsigned channel) /* Clear any SER */ edma_shadow0_write_array(ecc, SH_SECR, j, mask); edma_shadow0_write_array(ecc, SH_EESR, j, mask); - pr_debug("EDMA: EER%d %08x\n", j, - edma_shadow0_read_array(ecc, SH_EER, j)); + dev_dbg(ecc->dev, "EER%d %08x\n", j, + edma_shadow0_read_array(ecc, SH_EER, j)); return 0; } @@ -709,8 +709,8 @@ static void edma_stop(struct edma_cc *ecc, unsigned channel) /* clear possibly pending completion interrupt */ edma_shadow0_write_array(ecc, SH_ICR, j, mask); - pr_debug("EDMA: EER%d %08x\n", j, - edma_shadow0_read_array(ecc, SH_EER, j)); + dev_dbg(ecc->dev, "EER%d %08x\n", j, + edma_shadow0_read_array(ecc, SH_EER, j)); /* REVISIT: consider guarding against inappropriate event * chaining by overwriting with dummy_paramset. @@ -779,8 +779,8 @@ static int edma_trigger_channel(struct edma_cc *ecc, unsigned channel) edma_shadow0_write_array(ecc, SH_ESR, (channel >> 5), mask); - pr_debug("EDMA: ESR%d %08x\n", (channel >> 5), - edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5))); + dev_dbg(ecc->dev, "ESR%d %08x\n", (channel >> 5), + edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5))); return 0; } @@ -810,8 +810,8 @@ static void edma_clean_channel(struct edma_cc *ecc, unsigned channel) int j = (channel >> 5); unsigned int mask = BIT(channel & 0x1f); - pr_debug("EDMA: EMR%d %08x\n", j, - edma_read_array(ecc, EDMA_EMR, j)); + dev_dbg(ecc->dev, "EMR%d %08x\n", j, + edma_read_array(ecc, EDMA_EMR, j)); edma_shadow0_write_array(ecc, SH_ECR, j, mask); /* Clear the corresponding EMR bits */ edma_write_array(ecc, EDMA_EMCR, j, mask);