diff mbox

dmaengine: dw: fix a typo for bitfields of CTL_LO

Message ID 1452127173-11999-1-git-send-email-yang.jie@intel.com (mailing list archive)
State Accepted
Headers show

Commit Message

Jie, Yang Jan. 7, 2016, 12:39 a.m. UTC 
The offset of SINC should be 9, not 7, here fix this
typo.

Signed-off-by: Jie Yang <yang.jie@intel.com>
---
 drivers/dma/dw/regs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Andy Shevchenko Jan. 7, 2016, 8:03 a.m. UTC | #1 
On Thu, Jan 7, 2016 at 2:39 AM, Jie Yang <yang.jie@intel.com> wrote:
> The offset of SINC should be 9, not 7, here fix this
> typo.

Nice!
Acked-by: Andy Shevchenko <andy.shevchenko@gmail.com>

>
> Signed-off-by: Jie Yang <yang.jie@intel.com>
> ---
>  drivers/dma/dw/regs.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h
> index 241ff2b..0a50c18 100644
> --- a/drivers/dma/dw/regs.h
> +++ b/drivers/dma/dw/regs.h
> @@ -150,7 +150,7 @@ enum dw_dma_msize {
>  #define DWC_CTLL_DST_INC       (0<<7)          /* DAR update/not */
>  #define DWC_CTLL_DST_DEC       (1<<7)
>  #define DWC_CTLL_DST_FIX       (2<<7)
> -#define DWC_CTLL_SRC_INC       (0<<7)          /* SAR update/not */
> +#define DWC_CTLL_SRC_INC       (0<<9)          /* SAR update/not */
>  #define DWC_CTLL_SRC_DEC       (1<<9)
>  #define DWC_CTLL_SRC_FIX       (2<<9)
>  #define DWC_CTLL_DST_MSIZE(n)  ((n)<<11)       /* burst, #elements */
> --
> 2.5.0
>
Vinod Koul Jan. 13, 2016, 12:03 p.m. UTC | #2 
On Thu, Jan 07, 2016 at 08:39:33AM +0800, Jie Yang wrote:
> The offset of SINC should be 9, not 7, here fix this
> typo.
> 

Applied, thanks
diff mbox

Patch

diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h
index 241ff2b..0a50c18 100644
--- a/drivers/dma/dw/regs.h
+++ b/drivers/dma/dw/regs.h
@@ -150,7 +150,7 @@  enum dw_dma_msize {
 #define DWC_CTLL_DST_INC	(0<<7)		/* DAR update/not */
 #define DWC_CTLL_DST_DEC	(1<<7)
 #define DWC_CTLL_DST_FIX	(2<<7)
-#define DWC_CTLL_SRC_INC	(0<<7)		/* SAR update/not */
+#define DWC_CTLL_SRC_INC	(0<<9)		/* SAR update/not */
 #define DWC_CTLL_SRC_DEC	(1<<9)
 #define DWC_CTLL_SRC_FIX	(2<<9)
 #define DWC_CTLL_DST_MSIZE(n)	((n)<<11)	/* burst, #elements */