From patchwork Mon Apr 11 12:51:06 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 8800811 Return-Path: X-Original-To: patchwork-dmaengine@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E9E5DC0553 for ; Mon, 11 Apr 2016 12:54:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 16315202F8 for ; Mon, 11 Apr 2016 12:54:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1F7E520306 for ; Mon, 11 Apr 2016 12:54:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932225AbcDKMyh (ORCPT ); Mon, 11 Apr 2016 08:54:37 -0400 Received: from mga11.intel.com ([192.55.52.93]:35211 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754863AbcDKMvT (ORCPT ); Mon, 11 Apr 2016 08:51:19 -0400 Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP; 11 Apr 2016 05:51:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,462,1455004800"; d="scan'208";a="684363070" Received: from black.fi.intel.com ([10.237.72.93]) by FMSMGA003.fm.intel.com with ESMTP; 11 Apr 2016 05:51:18 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 3A889891; Mon, 11 Apr 2016 15:51:12 +0300 (EEST) From: Andy Shevchenko To: Bryan O'Donoghue , Peter Hurley , linux-serial@vger.kernel.org, Vinod Koul , linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, Greg Kroah-Hartman , ismo.puustinen@intel.com, Heikki Krogerus Cc: Andy Shevchenko Subject: [PATCH v2 06/11] serial: 8250_dma: adjust DMA address of the UART Date: Mon, 11 Apr 2016 15:51:06 +0300 Message-Id: <1460379071-132591-7-git-send-email-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.8.0.rc3 In-Reply-To: <1460379071-132591-1-git-send-email-andriy.shevchenko@linux.intel.com> References: <1460379071-132591-1-git-send-email-andriy.shevchenko@linux.intel.com> Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some UARTs, e.g. one is used in Intel Quark, have a different address base for DMA operations. Introduce an additional field (per RX and TX DMA channels) in struct uart_8250_dma to cover those cases. Signed-off-by: Andy Shevchenko Reviewed-by: Heikki Krogerus --- drivers/tty/serial/8250/8250.h | 5 +++++ drivers/tty/serial/8250/8250_dma.c | 8 ++++++-- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/8250/8250.h b/drivers/tty/serial/8250/8250.h index 047a7ba..526ed3e 100644 --- a/drivers/tty/serial/8250/8250.h +++ b/drivers/tty/serial/8250/8250.h @@ -31,6 +31,11 @@ struct uart_8250_dma { struct dma_chan *rxchan; struct dma_chan *txchan; + /* Device address base for DMA operations */ + phys_addr_t rx_dma_addr; + phys_addr_t tx_dma_addr; + + /* DMA address of the buffer in memory */ dma_addr_t rx_addr; dma_addr_t tx_addr; diff --git a/drivers/tty/serial/8250/8250_dma.c b/drivers/tty/serial/8250/8250_dma.c index 9d80bb1..1553181 100644 --- a/drivers/tty/serial/8250/8250_dma.c +++ b/drivers/tty/serial/8250/8250_dma.c @@ -157,16 +157,20 @@ int serial8250_rx_dma(struct uart_8250_port *p, unsigned int iir) int serial8250_request_dma(struct uart_8250_port *p) { struct uart_8250_dma *dma = p->dma; + phys_addr_t rx_dma_addr = dma->rx_dma_addr ? + dma->rx_dma_addr : p->port.mapbase; + phys_addr_t tx_dma_addr = dma->tx_dma_addr ? + dma->tx_dma_addr : p->port.mapbase; dma_cap_mask_t mask; /* Default slave configuration parameters */ dma->rxconf.direction = DMA_DEV_TO_MEM; dma->rxconf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; - dma->rxconf.src_addr = p->port.mapbase + UART_RX; + dma->rxconf.src_addr = rx_dma_addr + UART_RX; dma->txconf.direction = DMA_MEM_TO_DEV; dma->txconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; - dma->txconf.dst_addr = p->port.mapbase + UART_TX; + dma->txconf.dst_addr = tx_dma_addr + UART_TX; dma_cap_zero(mask); dma_cap_set(DMA_SLAVE, mask);