From patchwork Fri May 6 15:17:12 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 9033861 Return-Path: X-Original-To: patchwork-dmaengine@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 302039F30C for ; Fri, 6 May 2016 15:17:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4E00C2026F for ; Fri, 6 May 2016 15:17:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4AA66201BC for ; Fri, 6 May 2016 15:17:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757515AbcEFPR3 (ORCPT ); Fri, 6 May 2016 11:17:29 -0400 Received: from mga03.intel.com ([134.134.136.65]:26741 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757964AbcEFPR1 (ORCPT ); Fri, 6 May 2016 11:17:27 -0400 Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP; 06 May 2016 08:17:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,587,1455004800"; d="scan'208";a="98480082" Received: from black.fi.intel.com ([10.237.72.93]) by fmsmga004.fm.intel.com with ESMTP; 06 May 2016 08:17:23 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 5579842D; Fri, 6 May 2016 18:17:21 +0300 (EEST) From: Andy Shevchenko To: Bryan O'Donoghue , Peter Hurley , linux-serial@vger.kernel.org, Vinod Koul , linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, Greg Kroah-Hartman , ismo.puustinen@intel.com, Heikki Krogerus Cc: Andy Shevchenko Subject: [PATCH v5 03/11] dmaengine: dw: set polarity of handshake interface Date: Fri, 6 May 2016 18:17:12 +0300 Message-Id: <1462547840-14091-4-git-send-email-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1462547840-14091-1-git-send-email-andriy.shevchenko@linux.intel.com> References: <1462547840-14091-1-git-send-email-andriy.shevchenko@linux.intel.com> Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Spam-Status: No, score=-9.0 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Intel Quark UART uses DesignWare DMA IP. Though the DMA IP is connected in such way that handshake interface uses inverted polarity. We have to provide a possibility to set this in the DMA driver when configuring a channel. Introduce a new member of custom slave configuration called 'polarity' and set active low polarity in case this value is 'true'. Signed-off-by: Andy Shevchenko --- drivers/dma/dw/core.c | 4 ++++ include/linux/platform_data/dma-dw.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c index 81b06df..59f571c 100644 --- a/drivers/dma/dw/core.c +++ b/drivers/dma/dw/core.c @@ -150,6 +150,10 @@ static void dwc_initialize(struct dw_dma_chan *dwc) cfghi |= DWC_CFGH_DST_PER(dwc->dws.dst_id); cfghi |= DWC_CFGH_SRC_PER(dwc->dws.src_id); + /* Set polarity of handshake interface */ + cfglo |= dwc->dws.hs_polarity ? + DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL : 0; + channel_writel(dwc, CFG_LO, cfglo); channel_writel(dwc, CFG_HI, cfghi); diff --git a/include/linux/platform_data/dma-dw.h b/include/linux/platform_data/dma-dw.h index d15d8ba..4636c93 100644 --- a/include/linux/platform_data/dma-dw.h +++ b/include/linux/platform_data/dma-dw.h @@ -23,6 +23,7 @@ * @dst_id: dst request line * @m_master: memory master for transfers on allocated channel * @p_master: peripheral master for transfers on allocated channel + * @hs_polarity:set active low polarity of handshake interface */ struct dw_dma_slave { struct device *dma_dev; @@ -30,6 +31,7 @@ struct dw_dma_slave { u8 dst_id; u8 m_master; u8 p_master; + bool hs_polarity; }; /**