| Message ID | 1484926369-30910-4-git-send-email-andrea.merello@gmail.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
On Fri, Jan 20, 2017 at 04:32:48PM +0100, Andrea Merello wrote: > The maximumum trasfer length is currently hardcoded in the driver, but > it depends by how the soft-IP is actually configuried. /s/configuried/configured > This seems to affect also max possible length for SG transfers. > > This patch introduce a new DT property in order to operate with proper > maximum trasfer length. > > Signed-off-by: Andrea Merello <andrea.merello@gmail.com> > --- > drivers/dma/xilinx/xilinx_dma.c | 22 ++++++++++++++++------ > 1 file changed, 16 insertions(+), 6 deletions(-) > > diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c > index 33c0949..cbd8d8c 100644 > --- a/drivers/dma/xilinx/xilinx_dma.c > +++ b/drivers/dma/xilinx/xilinx_dma.c > @@ -409,6 +409,7 @@ struct xilinx_dma_device { > struct clk *rxs_clk; > u32 nr_channels; > u32 chan_id; > + int max_transfer; > }; > > /* Macros */ > @@ -1764,8 +1765,8 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg( > * the next chuck start address is aligned > */ > copy = sg_dma_len(sg) - sg_used; > - if (copy > XILINX_DMA_MAX_TRANS_LEN) > - copy = XILINX_DMA_MAX_TRANS_LEN & > + if (copy > chan->xdev->max_transfer) > + copy = chan->xdev->max_transfer & > chan->copy_mask; > > hw = &segment->hw; > @@ -1875,8 +1876,8 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic( > * the next chuck start address is aligned > */ > copy = period_len - sg_used; > - if (copy > XILINX_DMA_MAX_TRANS_LEN) > - copy = XILINX_DMA_MAX_TRANS_LEN & > + if (copy > chan->xdev->max_transfer) > + copy = chan->xdev->max_transfer & > chan->copy_mask; > > hw = &segment->hw; > @@ -2534,7 +2535,7 @@ static int xilinx_dma_probe(struct platform_device *pdev) > struct xilinx_dma_device *xdev; > struct device_node *child, *np = pdev->dev.of_node; > struct resource *io; > - u32 num_frames, addr_width; > + u32 num_frames, addr_width, lenreg_width; > int i, err; > > /* Allocate and initialize the DMA engine structure */ > @@ -2565,8 +2566,17 @@ static int xilinx_dma_probe(struct platform_device *pdev) > return PTR_ERR(xdev->regs); > > /* Retrieve the DMA engine properties from the device tree */ > - if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) > + if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { > xdev->mcdma = of_property_read_bool(node, "xlnx,mcdma"); > + err = of_property_read_u32(node, "xlnx,lengthregwidth", > + &lenreg_width); ah you are using a property for this, where is this added?? > + if (err < 0) { > + dev_err(xdev->dev, > + "missing xlnx,lengthregwidth property\n"); > + return err; > + } > + xdev->max_transfer = GENMASK(lenreg_width, 0); > + } > > if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { > err = of_property_read_u32(node, "xlnx,num-fstores", > -- > 2.7.4 >
> -----Original Message----- > From: dmaengine-owner@vger.kernel.org [mailto:dmaengine- > owner@vger.kernel.org] On Behalf Of Andrea Merello > Sent: Friday, January 20, 2017 9:03 PM > To: vinod.koul@intel.com; michal.simek@xilinx.com; Soren Brinkmann > <sorenb@xilinx.com> > Cc: dmaengine@vger.kernel.org; Andrea Merello > <andrea.merello@gmail.com> > Subject: [PATCH 4/5] dmaengine: xilinx_dma: fix hardcoded maximum transfer > length may be wrong Maybe a simpler commit msg - "Program hardware supported buffer length" > > The maximumum trasfer length is currently hardcoded in the driver, but > it depends by how the soft-IP is actually configuried. Fix typos in the description. > > This seems to affect also max possible length for SG transfers. > > This patch introduce a new DT property in order to operate with proper > maximum trasfer length. > > Signed-off-by: Andrea Merello <andrea.merello@gmail.com> > --- > drivers/dma/xilinx/xilinx_dma.c | 22 ++++++++++++++++------ > 1 file changed, 16 insertions(+), 6 deletions(-) > > diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c > index 33c0949..cbd8d8c 100644 > --- a/drivers/dma/xilinx/xilinx_dma.c > +++ b/drivers/dma/xilinx/xilinx_dma.c > @@ -409,6 +409,7 @@ struct xilinx_dma_device { > struct clk *rxs_clk; > u32 nr_channels; > u32 chan_id; > + int max_transfer; Kernel-doc documentation for max_transfer > }; > > /* Macros */ > @@ -1764,8 +1765,8 @@ static struct dma_async_tx_descriptor > *xilinx_dma_prep_slave_sg( > * the next chuck start address is aligned > */ > copy = sg_dma_len(sg) - sg_used; > - if (copy > XILINX_DMA_MAX_TRANS_LEN) > - copy = XILINX_DMA_MAX_TRANS_LEN & > + if (copy > chan->xdev->max_transfer) > + copy = chan->xdev->max_transfer & > chan->copy_mask; > > hw = &segment->hw; > @@ -1875,8 +1876,8 @@ static struct dma_async_tx_descriptor > *xilinx_dma_prep_dma_cyclic( > * the next chuck start address is aligned > */ > copy = period_len - sg_used; > - if (copy > XILINX_DMA_MAX_TRANS_LEN) > - copy = XILINX_DMA_MAX_TRANS_LEN & > + if (copy > chan->xdev->max_transfer) > + copy = chan->xdev->max_transfer & > chan->copy_mask; > > hw = &segment->hw; > @@ -2534,7 +2535,7 @@ static int xilinx_dma_probe(struct platform_device > *pdev) > struct xilinx_dma_device *xdev; > struct device_node *child, *np = pdev->dev.of_node; > struct resource *io; > - u32 num_frames, addr_width; > + u32 num_frames, addr_width, lenreg_width; > int i, err; > > /* Allocate and initialize the DMA engine structure */ > @@ -2565,8 +2566,17 @@ static int xilinx_dma_probe(struct platform_device > *pdev) > return PTR_ERR(xdev->regs); > > /* Retrieve the DMA engine properties from the device tree */ > - if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) > + if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { > xdev->mcdma = of_property_read_bool(node, "xlnx,mcdma"); > + err = of_property_read_u32(node, "xlnx,lengthregwidth", > + &lenreg_width); > + if (err < 0) { > + dev_err(xdev->dev, > + "missing xlnx,lengthregwidth property\n"); > + return err; Making it mandatory property will break DT backward compatibility unless a new compatible string is added. > + } > + xdev->max_transfer = GENMASK(lenreg_width, 0); > + } > > if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { > err = of_property_read_u32(node, "xlnx,num-fstores", > -- > 2.7.4 > > -- > To unsubscribe from this list: send the line "unsubscribe dmaengine" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html
Apparently you picked up a very old version of my patch - I didn't even remember that I've sent it already, otherwise I would have tagged today's one as "v2" - sorry. The updated one has a fix but, as you commented wrt PATCH 3/6, since this feature is already in Xilinx git tree, so I could either: - drop 3/6 and 4/6 from my series (and wait Xilinx's patch to will go on towards mainline by its own way). - adapt 3/6 to be consistent wrt Xilinx patch, drop 4/6 and replace it with the (rabased) Xilinx patch and resubmit in series v2 for mainlining. Please let me know what you prefer. On Wed, Jun 20, 2018 at 4:04 PM, Radhey Shyam Pandey <radheys@xilinx.com> wrote: >> -----Original Message----- >> From: dmaengine-owner@vger.kernel.org [mailto:dmaengine- >> owner@vger.kernel.org] On Behalf Of Andrea Merello >> Sent: Friday, January 20, 2017 9:03 PM >> To: vinod.koul@intel.com; michal.simek@xilinx.com; Soren Brinkmann >> <sorenb@xilinx.com> >> Cc: dmaengine@vger.kernel.org; Andrea Merello >> <andrea.merello@gmail.com> >> Subject: [PATCH 4/5] dmaengine: xilinx_dma: fix hardcoded maximum transfer >> length may be wrong > > Maybe a simpler commit msg - "Program hardware supported buffer length" >> >> The maximumum trasfer length is currently hardcoded in the driver, but >> it depends by how the soft-IP is actually configuried. > Fix typos in the description. > >> >> This seems to affect also max possible length for SG transfers. >> >> This patch introduce a new DT property in order to operate with proper >> maximum trasfer length. >> >> Signed-off-by: Andrea Merello <andrea.merello@gmail.com> >> --- >> drivers/dma/xilinx/xilinx_dma.c | 22 ++++++++++++++++------ >> 1 file changed, 16 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c >> index 33c0949..cbd8d8c 100644 >> --- a/drivers/dma/xilinx/xilinx_dma.c >> +++ b/drivers/dma/xilinx/xilinx_dma.c >> @@ -409,6 +409,7 @@ struct xilinx_dma_device { >> struct clk *rxs_clk; >> u32 nr_channels; >> u32 chan_id; >> + int max_transfer; > Kernel-doc documentation for max_transfer > >> }; >> >> /* Macros */ >> @@ -1764,8 +1765,8 @@ static struct dma_async_tx_descriptor >> *xilinx_dma_prep_slave_sg( >> * the next chuck start address is aligned >> */ >> copy = sg_dma_len(sg) - sg_used; >> - if (copy > XILINX_DMA_MAX_TRANS_LEN) >> - copy = XILINX_DMA_MAX_TRANS_LEN & >> + if (copy > chan->xdev->max_transfer) >> + copy = chan->xdev->max_transfer & >> chan->copy_mask; >> >> hw = &segment->hw; >> @@ -1875,8 +1876,8 @@ static struct dma_async_tx_descriptor >> *xilinx_dma_prep_dma_cyclic( >> * the next chuck start address is aligned >> */ >> copy = period_len - sg_used; >> - if (copy > XILINX_DMA_MAX_TRANS_LEN) >> - copy = XILINX_DMA_MAX_TRANS_LEN & >> + if (copy > chan->xdev->max_transfer) >> + copy = chan->xdev->max_transfer & >> chan->copy_mask; >> >> hw = &segment->hw; >> @@ -2534,7 +2535,7 @@ static int xilinx_dma_probe(struct platform_device >> *pdev) >> struct xilinx_dma_device *xdev; >> struct device_node *child, *np = pdev->dev.of_node; >> struct resource *io; >> - u32 num_frames, addr_width; >> + u32 num_frames, addr_width, lenreg_width; >> int i, err; >> >> /* Allocate and initialize the DMA engine structure */ >> @@ -2565,8 +2566,17 @@ static int xilinx_dma_probe(struct platform_device >> *pdev) >> return PTR_ERR(xdev->regs); >> >> /* Retrieve the DMA engine properties from the device tree */ >> - if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) >> + if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { >> xdev->mcdma = of_property_read_bool(node, "xlnx,mcdma"); >> + err = of_property_read_u32(node, "xlnx,lengthregwidth", >> + &lenreg_width); >> + if (err < 0) { >> + dev_err(xdev->dev, >> + "missing xlnx,lengthregwidth property\n"); >> + return err; > Making it mandatory property will break DT backward compatibility unless > a new compatible string is added. > >> + } >> + xdev->max_transfer = GENMASK(lenreg_width, 0); >> + } >> >> if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { >> err = of_property_read_u32(node, "xlnx,num-fstores", >> -- >> 2.7.4 >> >> -- >> To unsubscribe from this list: send the line "unsubscribe dmaengine" in >> the body of a message to majordomo@vger.kernel.org >> More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe dmaengine" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index 33c0949..cbd8d8c 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -409,6 +409,7 @@ struct xilinx_dma_device { struct clk *rxs_clk; u32 nr_channels; u32 chan_id; + int max_transfer; }; /* Macros */ @@ -1764,8 +1765,8 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg( * the next chuck start address is aligned */ copy = sg_dma_len(sg) - sg_used; - if (copy > XILINX_DMA_MAX_TRANS_LEN) - copy = XILINX_DMA_MAX_TRANS_LEN & + if (copy > chan->xdev->max_transfer) + copy = chan->xdev->max_transfer & chan->copy_mask; hw = &segment->hw; @@ -1875,8 +1876,8 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic( * the next chuck start address is aligned */ copy = period_len - sg_used; - if (copy > XILINX_DMA_MAX_TRANS_LEN) - copy = XILINX_DMA_MAX_TRANS_LEN & + if (copy > chan->xdev->max_transfer) + copy = chan->xdev->max_transfer & chan->copy_mask; hw = &segment->hw; @@ -2534,7 +2535,7 @@ static int xilinx_dma_probe(struct platform_device *pdev) struct xilinx_dma_device *xdev; struct device_node *child, *np = pdev->dev.of_node; struct resource *io; - u32 num_frames, addr_width; + u32 num_frames, addr_width, lenreg_width; int i, err; /* Allocate and initialize the DMA engine structure */ @@ -2565,8 +2566,17 @@ static int xilinx_dma_probe(struct platform_device *pdev) return PTR_ERR(xdev->regs); /* Retrieve the DMA engine properties from the device tree */ - if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) + if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { xdev->mcdma = of_property_read_bool(node, "xlnx,mcdma"); + err = of_property_read_u32(node, "xlnx,lengthregwidth", + &lenreg_width); + if (err < 0) { + dev_err(xdev->dev, + "missing xlnx,lengthregwidth property\n"); + return err; + } + xdev->max_transfer = GENMASK(lenreg_width, 0); + } if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { err = of_property_read_u32(node, "xlnx,num-fstores",
The maximumum trasfer length is currently hardcoded in the driver, but it depends by how the soft-IP is actually configuried. This seems to affect also max possible length for SG transfers. This patch introduce a new DT property in order to operate with proper maximum trasfer length. Signed-off-by: Andrea Merello <andrea.merello@gmail.com> --- drivers/dma/xilinx/xilinx_dma.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-)