From patchwork Fri Jan 20 15:32:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Merello X-Patchwork-Id: 9528827 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 78F67601AE for ; Fri, 20 Jan 2017 15:33:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6677828484 for ; Fri, 20 Jan 2017 15:33:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5A6E228687; Fri, 20 Jan 2017 15:33:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F069528484 for ; Fri, 20 Jan 2017 15:33:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752715AbdATPdL (ORCPT ); Fri, 20 Jan 2017 10:33:11 -0500 Received: from mail-wm0-f67.google.com ([74.125.82.67]:36453 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752689AbdATPdJ (ORCPT ); Fri, 20 Jan 2017 10:33:09 -0500 Received: by mail-wm0-f67.google.com with SMTP id r126so7506183wmr.3 for ; Fri, 20 Jan 2017 07:33:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=DeDHVUMxrR8QL+dfYfPFFgCRb2pjXCNzIYDQPAQFdN8=; b=mjT8a7MInTN5qSscJ6W+Tjwk0rEeg/OYgtKZxPCdu+zpc5nFpjkeekJ1gsu7nCALE0 XB2qJ8R5Yqdo5qmHWD6wWsv6e7OlgriLpUg3oPeMuZlYVhk772E1b5QlAuftloAHBbPp GnTRGBCcRcVJKHw0ff+IqXluGcvOQAUCSUDZEgmTx9eHA6JUg/DPV7JsnG5LcfkiNsNV 7hvi/XJU0/wMTiTpj1VFWQ1PlrQfKRz6Z1VZSy04s1/KBMUIy35CMC5QK2tRdMNZ1FMG fnH9W9sDOF3QKYum93MeITOb3NISCSvZO0CWqPhmpaI+bFtBehcH6e7BpRfge1oUEPBi K2/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DeDHVUMxrR8QL+dfYfPFFgCRb2pjXCNzIYDQPAQFdN8=; b=k/mDjP24+Hr7QRckrwCJIgOQOfVFPKDeG7Jyd1ZK4ipVAnggA6YzH5Wlj2C9ZfAMDp Dfktm/USQgj5BlTyJdoUuwyA2ZAOy+Ns1XXrc403rTO1bNwoNQGFnxlzQfP8knowirY/ +9RkuyuMTf75nvl72JcXJAKGwVNWfqxo6GJe38hYArUUgzX6WCjCzm0jEitJx90a6zeI GBiQNUtxGIgFS+ypxNOBbxQIRs5S17wJDQPYE9y8erG4NcACiVKGoqvKRaw+WnWGj5hB JfzdWm0wRxO71SYyp9eV+IGPEV6phh7j+wAwq23sDqGeEUB542ocbeZJbazsVx6pjuYx lODw== X-Gm-Message-State: AIkVDXLcCjk9OeZbrxygAGAKdpsv3BEwciHcx0/1q1+c0kLWJpmmniMKMYjskWRrStpqdQ== X-Received: by 10.28.94.8 with SMTP id s8mr3692763wmb.117.1484926383144; Fri, 20 Jan 2017 07:33:03 -0800 (PST) Received: from NewMoon.iit.local ([90.147.180.254]) by smtp.googlemail.com with ESMTPSA id l74sm6734899wmg.2.2017.01.20.07.33.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 20 Jan 2017 07:33:02 -0800 (PST) From: Andrea Merello To: vinod.koul@intel.com, michal.simek@xilinx.com, soren.brinkmann@xilinx.com Cc: dmaengine@vger.kernel.org, Andrea Merello Subject: [PATCH 4/5] dmaengine: xilinx_dma: fix hardcoded maximum transfer length may be wrong Date: Fri, 20 Jan 2017 16:32:48 +0100 Message-Id: <1484926369-30910-4-git-send-email-andrea.merello@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1484926369-30910-1-git-send-email-andrea.merello@gmail.com> References: <1484926369-30910-1-git-send-email-andrea.merello@gmail.com> Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The maximumum trasfer length is currently hardcoded in the driver, but it depends by how the soft-IP is actually configuried. This seems to affect also max possible length for SG transfers. This patch introduce a new DT property in order to operate with proper maximum trasfer length. Signed-off-by: Andrea Merello --- drivers/dma/xilinx/xilinx_dma.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index 33c0949..cbd8d8c 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -409,6 +409,7 @@ struct xilinx_dma_device { struct clk *rxs_clk; u32 nr_channels; u32 chan_id; + int max_transfer; }; /* Macros */ @@ -1764,8 +1765,8 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg( * the next chuck start address is aligned */ copy = sg_dma_len(sg) - sg_used; - if (copy > XILINX_DMA_MAX_TRANS_LEN) - copy = XILINX_DMA_MAX_TRANS_LEN & + if (copy > chan->xdev->max_transfer) + copy = chan->xdev->max_transfer & chan->copy_mask; hw = &segment->hw; @@ -1875,8 +1876,8 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic( * the next chuck start address is aligned */ copy = period_len - sg_used; - if (copy > XILINX_DMA_MAX_TRANS_LEN) - copy = XILINX_DMA_MAX_TRANS_LEN & + if (copy > chan->xdev->max_transfer) + copy = chan->xdev->max_transfer & chan->copy_mask; hw = &segment->hw; @@ -2534,7 +2535,7 @@ static int xilinx_dma_probe(struct platform_device *pdev) struct xilinx_dma_device *xdev; struct device_node *child, *np = pdev->dev.of_node; struct resource *io; - u32 num_frames, addr_width; + u32 num_frames, addr_width, lenreg_width; int i, err; /* Allocate and initialize the DMA engine structure */ @@ -2565,8 +2566,17 @@ static int xilinx_dma_probe(struct platform_device *pdev) return PTR_ERR(xdev->regs); /* Retrieve the DMA engine properties from the device tree */ - if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) + if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { xdev->mcdma = of_property_read_bool(node, "xlnx,mcdma"); + err = of_property_read_u32(node, "xlnx,lengthregwidth", + &lenreg_width); + if (err < 0) { + dev_err(xdev->dev, + "missing xlnx,lengthregwidth property\n"); + return err; + } + xdev->max_transfer = GENMASK(lenreg_width, 0); + } if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { err = of_property_read_u32(node, "xlnx,num-fstores",