| Message ID | 152874649737.37524.3174624852477335863.stgit@djiang5-desk3.ch.intel.com (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
On 11-06-18, 12:49, Dave Jiang wrote: > It seems that starting with Skylake Xeon, channel reset clears the > completion address register. Make sure the completion address register is > set again after reset. Applied, thanks
diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c index 8b5b23a8ace9..23fb2fa04000 100644 --- a/drivers/dma/ioat/dma.c +++ b/drivers/dma/ioat/dma.c @@ -688,6 +688,12 @@ static void ioat_restart_channel(struct ioatdma_chan *ioat_chan) { u64 phys_complete; + /* set the completion address register again */ + writel(lower_32_bits(ioat_chan->completion_dma), + ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW); + writel(upper_32_bits(ioat_chan->completion_dma), + ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH); + ioat_quiesce(ioat_chan, 0); if (ioat_cleanup_preamble(ioat_chan, &phys_complete)) __cleanup(ioat_chan, phys_complete);
It seems that starting with Skylake Xeon, channel reset clears the completion address register. Make sure the completion address register is set again after reset. Signed-off-by: Dave Jiang <dave.jiang@intel.com> --- v2: use lower_32_bits() and upper_32_bits() macro. (Sinan Kaya) drivers/dma/ioat/dma.c | 6 ++++++ 1 file changed, 6 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe dmaengine" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html