From patchwork Wed Dec 5 08:42:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Long Cheng X-Patchwork-Id: 10713275 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A11231731 for ; Wed, 5 Dec 2018 08:44:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 923A72851E for ; Wed, 5 Dec 2018 08:44:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 85D0F2B491; Wed, 5 Dec 2018 08:44:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3195E2851E for ; Wed, 5 Dec 2018 08:44:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727182AbeLEInx (ORCPT ); Wed, 5 Dec 2018 03:43:53 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:64593 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726924AbeLEInx (ORCPT ); Wed, 5 Dec 2018 03:43:53 -0500 X-UUID: f6d88bf2573f40bc81aa1900f3348e9c-20181205 X-UUID: f6d88bf2573f40bc81aa1900f3348e9c-20181205 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1187418380; Wed, 05 Dec 2018 16:43:39 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 5 Dec 2018 16:43:22 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 5 Dec 2018 16:43:21 +0800 From: Long Cheng To: Vinod Koul , Rob Herring , Mark Rutland CC: Matthias Brugger , Dan Williams , Greg Kroah-Hartman , Jiri Slaby , Sean Wang , Long Cheng , , , , , , , , Yingjoe Chen , YT Shen Subject: [PATCH v2 1/4] dt-bindings: dma: uart: add uart dma bindings Date: Wed, 5 Dec 2018 16:42:57 +0800 Message-ID: <1543999380-7946-2-git-send-email-long.cheng@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1543999380-7946-1-git-send-email-long.cheng@mediatek.com> References: <1543999380-7946-1-git-send-email-long.cheng@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 077C88C37235333F8E8FBFDEFE7CDB730C0B7FBE487852117541DCB7F1786BD92000:8 X-MTK: N Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP add uart dma bindings Signed-off-by: Long Cheng Reviewed-by: Rob Herring --- .../devicetree/bindings/dma/8250_mtk_dma.txt | 33 ++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/8250_mtk_dma.txt diff --git a/Documentation/devicetree/bindings/dma/8250_mtk_dma.txt b/Documentation/devicetree/bindings/dma/8250_mtk_dma.txt new file mode 100644 index 0000000..3fe0961 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/8250_mtk_dma.txt @@ -0,0 +1,33 @@ +* Mediatek UART APDMA Controller + +Required properties: +- compatible should contain: + * "mediatek,mt2712-uart-dma" for MT2712 compatible APDMA + * "mediatek,mt6577-uart-dma" for MT6577 and all of the above + +- reg: The base address of the APDMA register bank. + +- interrupts: A single interrupt specifier. + +- clocks : Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names: The APDMA clock for register accesses + +Examples: + + apdma: dma-controller@11000380 { + compatible = "mediatek,mt2712-uart-dma"; + reg = <0 0x11000380 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&pericfg CLK_PERI_AP_DMA>; + clock-names = "apdma"; + #dma-cells = <1>; + }; +